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ABSTRACT: The experimental results in this paper provide evidence of high-performance symmetric and emitter-down operation of SiGe-HBT's. SiGe-base transistors were fabricated by using Atmospheric-Pressure Chemical Vapor Deposition (APCVD) for the epitaxial growth of SiGe and Si layers, and a novel self-aligned device structure. Current gains of 2000 and 120, cutoff-frequencies of 64 GHz and 14 GHz, and maximum oscillation frequencies of 23 GHz and 10 GHz have been achieved for emitter-up and emitter-down operation, respectively.< >
IEEE Electron Device Letters 10/1994; · 2.85 Impact Factor
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ABSTRACT: A device isolation structure for low-parasitic bipolar transistor
integration is presented. The concept involves two selective epitaxial
growth steps (SEG) and two polishing cycles which replace the
collector-epitaxy and the deep/shallow trench formation in conventional
device isolation. With an optimum device layout, the collector-substrate
capacitance is reduced to ≃30%, the collector-base capacitance to
≃70%, and the extrinsic base contact resistance to <50% compared
to trench isolation. The combination of SEG and polishing makes it
possible to form SOI regions with locally different SOI thicknesses on
the same wafer, so that fully depleted CMOS and vertical bipolar
transistors can be combined in a SOI-BiCMOS technology
IEEE Transactions on Electron Devices 09/1994; · 2.32 Impact Factor
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VLSI Technology, 1993. Digest of Technical Papers. 1993 Symposium on; 02/1993
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D.L. Harame,
J.H. Comfort,
E.F. Crabbe,
J.D. Cressler,
J.D. Warnock,
B.S. Meyerson,
K.Y.J. Hsu,
J. Cotte, C.L. Stanis,
J.M.C. Stork,
J.Y.-C. Sun,
D.A. Danner,
P.D. Aanello
VLSI Technology, 1993. Digest of Technical Papers. 1993 Symposium on; 02/1993
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J.N. Burghartz,
J.D. Cressler,
J. Warnock,
R.C. McIntosh,
K.A. Jenkins,
J.Y.-C. Sun,
J.H. Comfort,
J.M.C. Stork, C.L. Stanis,
W. Lee,
D.D. Danner
[show abstract]
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ABSTRACT: A bipolar isolation structure with the capability of significantly reducing collector-base capacitance and base resistance is presented. Partial SOI, with SOI surrounding the collector opening, can be used to reduce the collector window width in combination with any emitter-base self-aligned bipolar device structure, and in particular for device structures that feature sublithographic emitter width. Near-ideal transistor Gummel characteristics and a minimum ECL gate delay of 24 ps have been achieved with a nonoptimized lateral device layout, and simulations suggest that sub-20-ps delay at reduced switch current will be possible by using the optimized partial-SOI isolation structure.< >
IEEE Electron Device Letters 09/1992; · 2.85 Impact Factor
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ABSTRACT: Two new types of narrow-emitter effects are identified in shallow
and narrow-junction polysilicon emitter bipolar transistors. These
effects result from a lower doping concentration close to the emitter
perimeter of large devices (perimeter depletion effect) or in
very-narrow-emitter devices where the polysilicon plugs up the emitter
window (emitter plug effect). The consequence is a locally shallower
emitter junction which causes a reduced collector current density and a
nonideal base current due to a partial overlap of the emitter-base
space-charge region with the poly/monosilicon interface. The nonuniform
doping in the polysilicon is verified by energy-dispersive X-ray
spectroscopy (EDX) measurements. Electrical measurements give a clear
indication of the emitter plug effect for two different self-aligned
transistor structures, and further evidence is given by a comparison of
various poly emitter processes
IEEE Transactions on Electron Devices 07/1992; · 2.32 Impact Factor
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ABSTRACT: The thermal relaxation of SiGe films deposited by ultrahigh‐vacuum chemical vapor deposition was studied by annealing the films for times up to 21/2 h at a temperature of 950 °C. Strain relaxation was determined by misfit dislocation density obtained by planar‐view transmission electron microscopy and by double‐crystal x‐ray diffractometry. When the relaxation process requires relatively few dislocations (≲2 μm), the films relax to a remnant strain which is in agreement with previous experimental measurements; however, when higher densities of misfit dislocations were generated, substantially larger remnant strains were observed. This is interpreted as resulting from energetic interactions among the dislocations and analyzed in terms of the theory developed previously. It is found that the cutoff distance for dislocation interactions is substantially greater than the film thickness and a value of 1.4±0.5 μm is determined for 75–150‐nm‐thick films. Limited data from the literature also indicate a cutoff distance that is substantially in excess of the film thickness. In addition, as the annealing time is increased, a marked propensity for dislocation banding is observed, attesting to the mixed nature (attractive and repulsive) of the interactions.
Journal of Applied Physics 06/1992; · 2.17 Impact Factor
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ABSTRACT: The role of dislocation‐dislocation interactions on the relaxation behavior of biaxially stressed semiconductor thin films is considered by including interaction terms in an energy minimization. Both parallel and crossing interactions are considered and energies are calculated for orthogonal arrays of equally spaced 60° misfit dislocations, and it is shown that the parallel interactions can be either attractive or repulsive. The equilibrium misfit dislocation density is shown to be a function of the ‘‘cutoff’’ distance for dislocation interactions in these structures.
Journal of Applied Physics 06/1992; · 2.17 Impact Factor
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ABSTRACT: An in-situ doped polysilicon emitter process for very shallow and narrow emitter formation and minimum emitter resistance is presented. An in-situ doped film was imbedded between two undoped poly spacer layers as a buried diffusion source (BDS) to reduce the emitter resistance and to form a high-quality poly/monosilicon interface. Transistors with an emitter area of 0.25 mu m*0.25 mu m and with nearly ideal I-V characteristics were fabricated. A cutoff frequency of 53 GHz and a minimum ECL gate delay of 26 ps were achieved using BDS poly emitter transistors with an emitter area of 0.35 mu m*4.0 mu m.< >
IEEE Electron Device Letters 01/1992; · 2.85 Impact Factor
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ABSTRACT: The feasibility of ion-implanting an intrinsic base into an
undoped strained SiGe-layer has been demonstrated by fabricating
self-aligned selective epitaxy emitter window (SEEW) PNP transistors
with ideal Gummel characteristics. Self-aligned SiGe base PNP
transistors have been achieved by ion-implanting and annealing arsenic
into undoped, stable SiGe layers. Ideal I - V
characteristics were achieved with both Si and SiGe base devices,
indicating that the implant damage was successfully annealed out. The
results demonstrate the feasibility of fabricating SiGe base structures
with a conventional ion-implanted approach
Bipolar Circuits and Technology Meeting, 1991., Proceedings of the 1991; 10/1991
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S. Verdonckt-Vandebroek,
E.F. Crabbe,
B.S. Meyerson,
D.L. Harame,
P.J. Restle,
J.M.C. Stork,
A.C. Megdanis, C.L. Stanis,
A.A. Bright,
G.M.W. Kroesen,
A.C. Warren
[show abstract]
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ABSTRACT: A novel subsurface SiGe-channel p-MOSFET is demonstrated in which modulation doping is used to control the threshold voltage without degrading the channel mobility. A novel device design consisting of a graded SiGe channel, an n/sup +/ polysilicon gate, and p/sup +/ modulation doping is used. A boron-doped layer is located underneath the graded and undoped SiGe channel to minimize process sensitivity and maximize transconductance. Low-field hole mobilities of 220 cm/sup 2//V-s at 300 K and 980 cm/sup 2//V-s at 82 K were achieved in functional submicrometer p-MOSFETs.< >
IEEE Electron Device Letters 09/1991; · 2.85 Impact Factor
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ABSTRACT: The thermal stability of SiGe films deposited by ultrahigh‐vacuum chemical vapor deposition was studied. Various Ge compositional profiles, including boxes, trapezoids, and triangles were examined. Planar‐view transmission electron microscopy was performed following growth and after furnace annealing at 950 °C for 30 min to determine the presence and density of misfit dislocations. All profiles showed very similar stability behavior when expressed in terms of the total thickness of the film, h eff , and the effective strain present in the layer, ϵ eff . Following the anneal, misfit dislocations were observed when h eff exceeded the critical thickness, as defined by Matthews and Blakeslee [J. Cryst. Growth 27, 118 (1974)], by a factor of ∼2.
Journal of Applied Physics 09/1991; · 2.17 Impact Factor
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S. Verdonckt-Vandebroek,
E.F. Crabbe,
B.S. Meyerson,
D.L. Harame,
P.J. Restle,
J.M.C. Stork,
A.C. Megdanis, C.L. Stanis,
A.A. Bright,
G.M.W. Kroesen,
A.C. Warren
VLSI Technology, 1991. Digest of Technical Papers., 1991 Symposium on; 06/1991
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D.L. Harame,
B.S. Meyerson,
E.F. Crabbe, C.L. Stanis,
J.M. Cotte,
J.M.C. Stork,
A.C. Megdanis,
G.L. Patton,
S.R. Stiffler,
J.B. Johnson,
J.D. Warnock,
J.H. Comfort,
J.Y.-C. Sun
VLSI Technology, 1991. Digest of Technical Papers., 1991 Symposium on; 06/1991
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ABSTRACT: A bipolar technology which allows for very thin base formation by
ultra-high vacuum/chemical vapor deposition (UHV/CVD) epitaxy and very
narrow emitter width using selective epitaxial overgrowth is presented.
The key step in this selective epitaxy emitter window (SEEW) process is
an in situ doped epitaxial lateral overgrowth over a thin and narrow
nitride/oxide pad which forms an emitter window in the sublithographic
range and provides an extrinsic base contact at the same time.
Advantages over conventional double-poly self-aligned technology are the
very thin epitaxial base, the formation of the extrinsic base after
intrinsic epitaxial base deposition resulting in a guaranteed link-up,
and an emitter width in the deep submicrometer range by optical
lithography. n-p-n bipolar transistors with 60-nm base width for 75
kΩ/□ intrinsic base resistance and emitter widths down to
0.2 μm with 0.07-μm tolerance (σ) have been fabricated using
SEEW technology. Nearly ideal I - V characteristics have
been achieved for these very narrow emitters. High-yield figures are
demonstrated. The SEEW structure can provide very high current density
at acceptable power level
IEEE Transactions on Electron Devices 03/1991; · 2.32 Impact Factor
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D.L. Harame,
J.M.C. Stork,
B.S. Meyerson,
E.F. Crabbe,
G.J. Scilla,
E. de Fresart,
A.E. Megdanis, C.L. Stanis,
G.L. Patton,
J.H. Comfort,
A.A. Bright,
J.B. Johnson,
S.S. Furkay
[show abstract]
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ABSTRACT: The AC performance of SiGe-base PNP transistors has been limited
by a valence band barrier at the base-collector junction caused by the
retrograde Ge profile. A two-times improvement in f <sub>T</sub>
over previous work on SiGe-base PNPs is reported. The improvement was
achieved by using a narrow base profile ( W <sub>B</sub>=50 nm)
and by grading the Ge across the neutral base and in the base-collector
junction (the retrograde Ge profile). Similar results ( f <sub>T
</sub>=30 GHz) were achieved for both polysilicon emitter and
single-crystal emitter PNP transistors with the same Ge retrograde
profile. The position of the retrograde Ge profile in the base-collector
junction was controlled by a self-aligned channeled boron implant
through the SiGe base. Numerical simulations demonstrate that the peak
f <sub>T</sub> is very sensitive to the retrograde Ge position
with respect to the base-collector doping profiles
Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International; 01/1991
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[show abstract]
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ABSTRACT: In the device a SiGe epitaxial base is integrated in a structure which uses in situ doped epitaxial lateral overgrowth for the formation of the emitter window and the extrinsic base contact. Nearly ideal I-V characteristics have been achieved for a base width of 60 nm with an intrinsic base resistance of 4.6 k Omega / Square Operator and for emitter widths down to 0.4 mu m. A DC collector current enhancement factor of 3.1 was obtained relative to a Si homojunction transistor with a 1.25 times higher intrinsic base resistance. The breakdown voltage BV/sub CBO/ is identical for both Si and SiGe devices, even though the collector-base depletion region is partly overlapped with the reduced-bandgap SiGe strained layer. The lower BV/sub CEO/, measured for the SiGe-base transistor, is due to the higher current gain. Based on these results the fabrication of high-speed bipolar circuits that take advantage of SiGe-base bandgap engineering seems possible using selective epitaxy emitter window (SEEW) technology.< >
IEEE Electron Device Letters 08/1990; · 2.85 Impact Factor
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ABSTRACT: The scaling limits of nonplanar polysilicon emitters are studied
by fabricating and measuring NPN transistors with emitter depths between
10 nm and 25 nm, with emitter widths down to 0.2 μm, and with an
epitaxial base as narrow as 50 nm. Excellent device characteristics can
be achieved for an emitter depth of 25 nm. Transistors with shallower
emitters are degraded by an arsenic depletion at the emitter perimeter
and by plugging of the polysilicon in very narrow emitters. The dopant
depletion at the perimeter for wide and plugged emitters has been
verified by energy-dispersive X-ray spectroscopy (EDX) measurements.
Additional rapid thermal annealing (RTA) gives more uniform dopant
distribution and a nondegraded transistor with a 0.2 μm-wide, 20
nm-deep poly emitter. It is thought desirable to scale down the emitter
poly thickness, to reduce the emitter topography, or to use in situ
doping in order to overcome the perimeter and plug effects in very
narrow bipolar transistors
VLSI Technology, 1990. Digest of Technical Papers.1990 Symposium on; 07/1990
