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F. Bedeschi,
R. Fackenthal, C. Resta,
E.M. Donze,
M. Jagasivamani,
E.C. Buda,
F. Pellizzer,
D.W. Chow,
A. Cabrini,
G. Calvi,
R. Faravelli,
A. Fantini,
G. Torelli,
D. Mills,
R. Gastaldi,
G. Casagrande
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ABSTRACT: In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change Ge<sub>2</sub>-Sb<sub>2</sub>-TeB alloy is presented. Memory cells are bipolar selected, and are based on a /xtrench architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distribu tions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150 degC bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same mutrench cell structure.
IEEE Journal of Solid-State Circuits 02/2009; · 3.23 Impact Factor
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F. Bedeschi,
R. Fackenthal, C. Resta,
E.M. Donze,
M. Jagasivamani,
E. Buda,
F. Pellizzer,
D. Chow,
A. Cabrini,
G.M.A. Calvi,
R. Faravelli,
A. Fantini,
G. Torelli,
Duane Mills,
R. Gastaldi,
G. Casagrande
[show abstract]
[hide abstract]
ABSTRACT: Phase-change memory (PCM) is becoming widely recognized as the most likely candidate to unify the many memory technologies that exist today (Lee, et al., 2007). The combination of non-volatile attributes of flash, RAM-like bit-alterability, and fast reads and writes position PCM to enable changes in the memory subsystems of cellular phones, PCs and countless embedded and consumer electronics applications. This design's multi-level cell (MLC) capabilities combined with long- term scalability reduce PCM costs as only realized before by hard disk drives. MLC technology is challenged with fitting more cell states (4 in the case of 2 bit per cell), along with distribution spreads due to process, design, and environmental variations, within a limited window. We describe a 256Mb MLC test-chip in a 90nm micro-trench (mutrench) PCM technology, and MLC endurance results from an 8Mb 0.18mum PCM test-chip with the same trench cell structure. A program algorithm achieving tightly placed inner states and experimental results illustrating distinct current distributions are presented to demonstrate MLC capability.
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International; 03/2008
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F. Bedeschi,
R. Bez,
C. Boffino,
E. Bonizzoni,
E.C. Buda,
G. Casagrande,
L. Costa,
M. Ferraro,
R. Gastaldi,
O. Khouri,
F. Ottogalli,
F. Pellizzer,
A. Pirovano, C. Resta,
G. Torelli,
M. Tosi
[show abstract]
[hide abstract]
ABSTRACT: A μtrench Phase-Change Memory (PCM) cell with MOSFET selector and its integration in a 4-Mb experimental chip fabricated in 0.18-μm CMOS technology are presented. A cascode bitline biasing scheme allows read and write voltages to be fed to the addressed storage elements with the required accuracy. The high-performance capabilities of PCM cells were experimentally investigated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to NOR Flash memories. Programmed cell current distributions on the 4-Mb array demonstrate an adequate working window and, together with first endurance measurements, assess the feasibility of PCMs in standard CMOS technology with few additional process modules.
IEEE Journal of Solid-State Circuits 08/2005; · 3.23 Impact Factor
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F. Bedeschi,
R. Bez,
C. Boffino,
E. Bonizzoni,
E. Buda,
G. Casagrande,
L. Costa,
M. Ferraro,
R. Gastaldi,
O. Khouri,
F. Ottogalli,
F. Pellizzer,
A. Pirovano, C. Resta,
G. Torelli,
M. Tosi
[show abstract]
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ABSTRACT: This paper presents a 4-Mb phase-change memory experimental chip using an MOS transistor as a cell selector. A cascode bit-line biasing scheme allows read and write voltages to be fed to the storage element with adequate accuracy. The chip was integrated with 3-V 0.18-μm CMOS technology and experimentally evaluated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to present NOR Flash memories. Cell current distributions on the 4-Mb array proved chip functionality and a good working window, thus demonstrating the feasibility of a stand-alone phase-change memory with standard CMOS fabrication process.
Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European; 10/2004
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F. Bedeschi, C. Resta,
O. Khouri,
E. Buda,
L. Costa,
M. Ferraro,
F. Pellizzer,
F. Ottogalli,
A. Pirovano,
M. Tosi,
R. Bez,
R. Gastaldi,
G. Casagrande
[show abstract]
[hide abstract]
ABSTRACT: An 8Mb Non-Volatile Memory Demonstrator incorporating a novel 0.32 μm<sup>2</sup> Phase-Change Memory (PCM) cell using a Bipolar Junction Transistor (BJT) as selector and integrated into a 3V 0.18 μm CMOS technology is presented. Realistically large 4Mb tiles with a voltage regulation scheme that allows fast bitline precharge and sense are proposed. An innovative approach that minimizes the array leakage has been used to verify the feasibility of high-density PCM memories with improved Read/Write performance compared to Flash. Finally, cells distributions and first endurance measurements demonstrate the chip functionality and a good working window.
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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ABSTRACT: A low-power low-voltage MOSFET-only voltage reference featuring very good temperature stability and referred to the positive power supply is proposed. It compensates for the temperature dependence of a gate-to-source voltage of an MOS transistor working in the weak inversion region with a proportional-to-absolute-temperature voltage generated by a pair of MOS devices operating in the same region. The circuit, designed for a 0.35-μm (0.18-μm in the memory array) CMOS flash memory technology, can operate with supply voltage as low as 1 V and draws a current of 3 μA. The simulated variation of the reference voltage is within 0.2% over the range from -20 to 80°C.
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on; 06/2004
