Arne Linde

Chalmers University of Technology, Goeteborg, Västra Götaland, Sweden

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Publications (7)0 Total impact

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    ABSTRACT: The goal of the REMAP project was to gain new knowledge about the design and use of massively parallel computer architectures in embedded real-time systems. In order to support adaptive and learning behavior in such systems, the efficient execution of Artificial Neural Network (ANN) algorithms on regular processor arrays was in focus. The REMAP-β parallel computer built in the project was designed with ANN computations as the main target application area. This chapter gives an overview of the computational requirements found in ANN algorithms in general and motivates the use of regular processor arrays for the efficient execution of such algorithms. REMAP-β was implemented using the FPGA circuits that were available around 1990. The architecture, following the SIMD principle (Single Instruction stream, Multiple Data streams), is described, as well as the mapping of some important and representative ANN algorithms. Implemented in FPGA, the system served as an architecture laboratory. Variations of the architecture are discussed, as well as scalability of fully synchronous SIMD architectures. The design principles of a VLSI-implemented successor of REMAP-β are described, and the paper is concluded with a discussion of how the more powerful FPGA circuits of today could be used in a similar architecture.
    10/2006: pages 325-360;
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    International Conference on Artificial Neural Networks ICANN 98; 10/1998
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    ABSTRACT: To optimize the performance and reduce the emission levels of an internal combustion engine one needs some measurements of the combustion process duality. We propose two artificial neural network models which use the ionization current for estimation of the position of the pressure peak and the air-fuel ratio. The pressure peak position model produces estimates on a cycle-by-cycle basis for each of the cylinders. These estimates are twice as good as estimates obtained from a linear model. The air-fuel ratio model uses the universal exhaust gas oxygen sensor as reference; it produces estimates that are ten times better than estimates obtained from a linear model
    Intelligent Transportation System, 1997. ITSC '97., IEEE Conference on; 12/1997
  • Arne Linde, Mikael Taveniku
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    ABSTRACT: In REMAP, the Real-time, Embedded, Modular Adaptive massively Parallel Processor Project, the focus is on the design of processor array modules and the mapping of Artificial Neural Network computations on them. The paper describes the structure and possibilities of a SIMD computing platform (the REMAP b). The REMAP b is a prototype platform that utilizes dynamically programmable logic cell arrays, the flexibility of them allows for architectural experimentation with the modules. An Architecture Laboratory The machine is a SIMD (Single Instruction Multiple Data) organized architecture meaning that a large number of Processing Elements (PEs) are working in parallel with different data, but all doing the same operations on it. All PEs are connected to the same Control Unit[1]. Which broadcasts the microinstruction and memory address plus the system clock to all PEs in the system. The microinstructions are executed one each clock cycle, they are low-level one-bit operations such as ADD, ...
    11/1997;
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    ABSTRACT: To be able to meet the demands of tomorrow on lower emissions from small two-stroke engines, used e.g. in chain-saws, there is a need to enhance the control over the combustion. One interesting parameter is the air-to-fuel ratio (A/F). If A/F can be measured, then it is possible to intelligently control the fuel, and thus obtain a desired A/F. This is interesting in combustion engine control, by the fact that the emissions and the power from the engine directly depend on the current A/F. Most of the larger engines mounted in automobiles today have a sensor (the so called lambda-sensor) measuring A/F in the exhausts. This sensor has a number of problems: it is expensive, slow, sensitive to pollution and, most important of all, it gives only a binary output (indicating whether A/F is above or below a factory set value). With this background, it is motivated to seek for other ways of measuring A/F. In this study a method using ion-current measurements and artificial neural networks to est...
    11/1997;
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    ABSTRACT: Highly parallel processor arrays will be useful components in advanced industrial real-time systems in the future. Especially in applications where the interaction with the environment utilizes visual, auditory, or tactile sensory units and advanced motor units massive parallelism is required. The possibility of making trainable systems by the use of artificial neural network (ANN) models is appealing in this context. In REMAP 3 , the Reconfigurable, Embedded, Massively Parallel Processor Project, the focus is on the design of processor array modules and the mapping of ANN computations on these modules. The paper describes the structure of the first prototype which utilizes dynamically programmable logic cell arrays to allow architectural experimentation with the modules. Examples of processing element architectures are given. Low-level programming is described. Presented at DSA-92, the Fourth Swedish Workshop on Computer System Architecture, Linköping, Sweden 13-15 January 2 1 THE...
    11/1997;
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    ABSTRACT: With the arrival of large Field Programmable Gate Arrays (FPGAs) it is possible to build an entire computer using only FPGA and memory. In this paper we share some experience from building a highly parallel computer using this concept. Even if today's FPGAs are of considerable size, each processor must be relatively simple if a highly parallel computer is to be constructed from them. Based on our experience of other parallel computers and thorough studies of the intended applications, we think it is possible to build very powerful and efficient computers using bit-serial processing elements with SIMD (Single Instruction stream, Multiple Data streams) control.
    Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31 - September 2, 1992, Selected Papers; 01/1992