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ABSTRACT: This work proposes a novel p -type boron-doped floating gate for n -channel split-gate flash memory. A lower program voltage, with a programming time of 7 μ s , results in five times of the conventional source-side injection programming efficiency, a 5% wider program/erase window, and more reliable endurance characteristics. Additionally, a 2 Mbit embedded flash Intellectual Property (IP) has been successfully implemented and statistically compared. The lower program voltage reduces concerns around the high-voltage decoder, the charge pump efficiency, and the array efficiency beyond 90 nm nodes. The new p -doped split-gate structure provides a very promising solution for advanced embedded split-gate flash memory beyond the 90 nm node.
Applied Physics Letters 12/2008; · 3.84 Impact Factor
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ABSTRACT: Analytical program disturb modeling of split gate flash is presented for the first time and used to estimate post-cycling time to disturb by formulating punch through current evolution with cycling. The optimized erase voltage is chosen to achieve maximum endurance based on tradeoff of erase time pushout and post-cycling program disturb. The early punch through failure mechanism of array cycling is thus understood and eliminated by new-proposed STI corner shape
Reliability physics symposium, 2007. proceedings. 45th annual. ieee international; 05/2007
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ABSTRACT: In developing an accurate lifetime-prediction model for postcycling data-retention failure rate of split-gate Flash memories, a floating-gate potential extraction method from the measured bit-cell-current data is proposed. Stress-induced leakage current through the coupling oxide caused by the source-side channel hot electron injection during program operation is the major cause for postcycling data-retention failure bits. Considering charge conservation and trap-assist-tunneling leakage current, the charge-gain behavior under low-temperature bake is modeled and the failure rate under various measured conditions can be predicted precisely. We have found that data-retention lifetime decreases as program/erase (P/E) cycling increases, while failing bits increase with numbers of P/E cycling.
IEEE Transactions on Device and Materials Reliability 04/2006; · 1.54 Impact Factor
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Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International; 02/2005
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Microelectronics Reliability. 01/2005; 45:1331-1336.
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ABSTRACT: In developing a precise model for post-cycling data retention failure rate of split-gate flash memories, a statistical method is proposed for the extraction of the floating-gate potential from the measured bit-cell-current data. Floating gate charge leakage mechanism during retention of split-gate flash memories is investigated as well. While multiple leakage mechanisms maybe the responsible for the failure bits in stack-gate flash memories, it is found that stress induced leakage current is the major cause for post-cycling data retention failure bits in split-gate flash memories.
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International; 05/2004
