A.W.S. Ross

The University of Edinburgh, Edinburgh, SCT, United Kingdom

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Publications (19)7.38 Total impact

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    ABSTRACT: The novel overlay test structure reported in this paper was purposely designed to serve as an application-specific reference material. It features standard frame-in-frame optical overlay targets embedded in electrical test features and fabricated by the same process as the parts being manufactured. Optical overlay is commonly used in process control applications due to its utility for determining the relative positions of features patterned in photoresist. Electrical overlay, although it can only be measured on fully patterned test structures, is the metric of interest. Using this combined optical/electrical overlay test structure, we can derive the relationship between the routinely measured optical overlay and the electrical overlay for any specific combination of process and optical overlay tool.
    Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on; 04/2007
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    ABSTRACT: Test structures have been fabricated to allow electrical critical dimensions (ECD) to be extracted from copper features with dimensions comparable to those replicated in IC interconnect systems. The implementation of these structures is such that no conductive barrier metal has been used. The advantage of this approach is that the electrical measurements provide a non-destructive and efficient method for determining CD values and for enabling fundamental studies of electron transport in narrow copper features unaffected by the complications of barrier metal films. This paper reports on the results of various tests which have been conducted to evaluate the current design.
    Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on; 04/2007
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    ABSTRACT: This paper discusses the main issues associated with integrating electrode controlled droplet motion using electro wetting on dielectric (EWOD) with IC foundry technology. The motivation behind this approach is based upon the desire to increase the number of control electrodes, which requires the implementation of on-chip line-column microelectronics. Increasing the number of electrodes is attractive as it provides the opportunity to finely adjust droplet size, and also increases the number of droplets that can be individually moved simultaneously. The tradeoffs associated with minimising the drive voltage by appropriate choice of dielectric thickness, strength and permittivity, are discussed and examples presented of systems with the ability to move liquid droplets using voltages between 27 and 70V. A small electrode array has been designed using transistors with high voltage shields using a 100V CMOS process. This circuitry has been fabricated and can successfully apply 90V to the electrodes. The paper presents the considerations related to the chip design and the issues associated with EWOD post-processing and the microfluidic packaging requirements.
    MEMS Sensors and Actuators, 2006. The Institution of Engineering and Technology Seminar on; 05/2006
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    ABSTRACT: A novel copper damascene process is reported for fabrication of electrical critical dimension (ECD) reference material. The method of fabrication first creates an initial "silicon preform" whose linewidth is transferred into a trench using a silicon nitride mould. The trench is created by removing a portion of the silicon and replacing it with copper to enable both transmission electron microscopy (TEM) and electrical linewidth measurements to be made on the same structure. The technique is based on the use of anisotropic wet etching of [110] silicon wafers to yield silicon features with vertical sidewalls. The paper demonstrates that this method successfully produces copper lines which serve as ECD control structures and the process can be applied to any damascene compatible material for developing electrical linewidth measurement reference material.
    Microelectronic Test Structures, 2006. ICMTS 2006. IEEE International Conference on; 04/2006
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    ABSTRACT: Atomic force and scanning electron microscope measurements of electrical structures for the measurement of critical dimension on alternating aperture phase shifting masks are presented. These have been used to explain anomalies that were observed in previously reported work. In addition, the development of a new capacitance test structure which can measure the alignment between the chrome blocking layer and the phase shifting areas etched into the quartz mask substrate is presented. A progressional offset array technique enables the use of this test structure without calibration and this is demonstrated by simulation and measurements.
    IEEE Transactions on Semiconductor Manufacturing 06/2005; DOI:10.1109/TSM.2005.845056 · 0.98 Impact Factor
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    ABSTRACT: Electrical test structures have been designed that are compatible with a standard alternating aperture, phase-shift mask manufacturing process. Measurements indicate that these have superior performance to previous designs where Greek cross structures suffered from asymmetry problems. As a result, the new test structures extract a consistent, and accurate, sheet resistance. In addition, the measurements on linewidth structures have demonstrated an improved capability with the CD offset variability being reduced to a quarter of the previous value. Electrical CD results from a wide range of test structures, both phase-shifted and binary, are presented and it is demonstrated that the phase-shifting elements have a negligible effect on the measurements. A limited number of atomic force microscope measurements have also been made for comparison purposes.
    Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on; 05/2005
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    ABSTRACT: A novel method is reported to measure the sheet resistance of materials that are incompatible with a CMOS process, using suspended polysilicon Greek cross test structures. To demonstrate the technique, gold (Au) was blanket evaporated in various thicknesses onto the test structures and the sheet resistance extracted. Sheet resistances ranging from 0.30Ω/&square;to 0.10Ω/&square;were measured for the deposited Au films on Greek cross structures with arm widths ranging between 5 and 20 μm. The extracted resistivity of 4.85×10<sup>-8</sup>Ωm agrees with values found in the literature (3.0×10<sup>-8</sup>Ωm-5.0×10<sup>-8</sup>Ωm) demonstrating that the structures are fully capable of measuring sheet resistance of blanket deposited films.
    Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on; 05/2005
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    ABSTRACT: The ability to test and characterise advanced photomasks for verification and process control is increasingly important and this paper builds on previous work in this area. Atomic force and scanning electron microscope measurements are used to explain anomalies in previously presented results. In addition, a new test structure has been developed to measure an important parameter in alternating aperture phase shifting masks: the alignment between the chrome blocking features and the phase shifting regions etched into the quartz substrate. Simulation results are presented which demonstrate the capability of the test structure when used in a progressional offset array.
    Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on; 04/2004
  • NanoMed 2004 - 4th International Workshop on Biomedical Applications of Nanotechnology; 01/2004
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    ABSTRACT: Focused ion beam (FIB) systems are commonly used to image, repair and modify integrated circuits by cutting holes in passivation to create vias or to selectively break metal tracks. The ion beam can also be used to deposit a metal, such as platinum, to create new connections. These techniques are very useful tools for debugging designs and testing possible changes to the circuit without the expense of new mask sets or silicon. This paper presents test structures which can be used to characterize a FIB induced platinum deposition process. Sheet resistance test structures have been fabricated using a FIB tool and the results of testing these structures are presented. The sheet resistance data has been used to fabricate platinum straps with a known resistance. This extends the capability of the focused ion beam system beyond the deposition of simple conducting straps. The design of the test structures has been improved through the use of current flow simulation to investigate the effects of geometry and misalignment on the measurement accuracy. The results of these simulations are also presented.
    IEEE Transactions on Semiconductor Manufacturing 06/2003; 16(2-16):199 - 206. DOI:10.1109/TSM.2003.811580 · 0.98 Impact Factor
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    ABSTRACT: The effects of the barrier layer and dishing in copper interconnects lead to extra difficulties in measuring sheet resistance (R<sub>S</sub>) and linewidth when compared with equivalent measurements on nondamascene tracks. This paper examines these issues and presents the results of simulations that quantify the effects of diffusion barrier layers and dishing on the extraction of R<sub>S</sub> from cross type test structures and the effect this has on linewidth measurement
    IEEE Transactions on Semiconductor Manufacturing 06/2002; DOI:10.1109/66.999595 · 0.98 Impact Factor
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    ABSTRACT: Focused Ion Beam (FIB) systems are commonly used to image, repair and modify integrated circuits by cutting holes in passivation to create vias or to selectively break metal tracks. The ion beam can also be used to deposit a metal, such as platinum, to create new connections. These techniques are very useful tools for debugging designs and testing possible changes to the circuit without the expense of new mask sets or silicon. This paper presents test structures to characterise a FIB platinum deposition process. Sheet resistance test structures have been fabricated using a FIB tool and the results of testing these structures are presented. This data will enable resistors with a known value to be fabricated in addition to conducting straps.
    Microelectronic Test Structures, 2002. ICMTS 2002. Proceedings of the 2002 International Conference on; 05/2002
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    ABSTRACT: The effect of the barrier layer and dishing in copper interconnects causes extra difficulties in measuring sheet resistance and linewidth when compared with equivalent measurements on nondamascene processed tracks. This paper examines these issues and, for the first time, quantifies the effects of diffusion barrier layers and CMP dishing on the extraction of R<sub>s</sub> from Greek cross type structures and the effect this has on linewidth measurement
    Microelectronic Test Structures, 2001. ICMTS 2001. Proceedings of the 2001 International Conference on; 02/2001
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    ABSTRACT: The critical dimensions required for 1 Gbit semiconductor technology will be beyond the capabilities of optical lithography. The laser-generated plasma X-ray source provides an alternative to synchrotron radiation for lithography, providing a quasi point source of radiation at ~1 nm wavelength. The 180 nm lithography required for 1 Gbit has been demonstrated by exposure of a novel commercial resist using a laboratory prototype plasma X-ray source. A MOSFET with 200 nm gate length has been produced using the new technology in mix-and-match with conventional methods. The device shows good electrical characteristics, demonstrating the promise of this approach
    Electronics Letters 01/1996; 31(25-31):2218 - 2219. DOI:10.1049/el:19951462 · 1.07 Impact Factor
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    ABSTRACT: The laser-plasma X-ray source at the Rutherford Appleton Laboratory has been used in a series of preliminary lithography trials in order to establish the feasibility of using this source for deep submicron device fabrication. These trials have provided a demonstration of photoresist linewidths down to 130nm and functional silicon FETs have been produced with 200nm gate electrodes. These devices show peak transconductances of 220mS/mm and 100mS/mm for n-channel and p-channel cases respectively. This paper summarises the lithographic procedures and resulting device characteristics.
    Microelectronic Engineering 01/1996; 30(1):187-190. DOI:10.1016/0167-9317(95)00223-5 · 1.34 Impact Factor
  • M. Fallon · A.J. Walton · J.T.M. Stevenson · A.W.S. Ross
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    ABSTRACT: A test structure is described which can be used to optimize the focus of wafer steppers. Simulation is used to examine the effect that some of the design parameters have on the sensitivity of the structure. Finally some practical measurements are presented
    IEEE Transactions on Semiconductor Manufacturing 09/1994; DOI:10.1109/66.311329 · 0.98 Impact Factor
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    ABSTRACT: The performance of the Gaudi structure has been examined and its sensitivity to dimensional variation is demonstrated. It has been shown that the effect of variation in resistivity and etch can be minimised by grouping the structures close together. This procedure has been used to optimise the focus setting using the Gaudi structure. A modified Gaudi test structure that is more sensitive to dimensional changes is also proposed. It consists of a single layer of polysilicon, the resistance of which is modulated by changes in resolution. Its sensitivity is maximised as the resolution approaches perfection making it ideally suited to optimising the setup of wafer steppers for small geometry processes
    Microelectronic Test Structures, 1994. ICMTS 1994. Proceedings of the 1994 International Conference on; 04/1994
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    ABSTRACT: A test structure that can be used for optimising the focus and exposure of wafer steppers is presented. It consists of a single layer of polysilicon which lends itself to automatic electrical measurement and does not suffer from the apex height reduction which occurs with the previously reported Gaudi structure.< >
    Electronics Letters 09/1993; 29(17-29):1573 - 1574. DOI:10.1049/el:19931048 · 1.07 Impact Factor
  • A.J. Walton · M Fallon · J.T.M. Stevenson · A.W.S. Ross
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    ABSTRACT: A test structure which can be used to optimize the focus of wafer steppers is described. Simulation is used to determine the optimum setting for some of the design parameters in order to ensure maximum sensitivity of the device. Preliminary results indicate that the resistance of the structure is sensitive to changes in both exposure and focus, but that the `noise' on the measurement masks the true sensitivity
    Microelectronic Test Structures, 1993. ICMTS 1993. Proceedings of the 1993 International Conference on; 04/1993