Publications (13)5.79 Total impact
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Article: The Merger board of the CDF Silicon Vertex Tracker
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ABSTRACT: The Merger board is part of the Silicon Vertex Tracker (SVT), a device dedicated to perform real-time track reconstruction with offline-like resolution and high efficiency at the Level 2 trigger of the CDF experiment. The Merger is a custom 9U × 400 mm VME board, running at an internal clock frequency of 33 MHz. Its main functional task in SVT is to merge up to four independent data streams into a single one. The merging operation can be performed on a first come, first served basis or according to an ordered sequence. There are four input streams and two identical output streams, so that the Merger also serves as a data fanout function. The board implements detailed error handling and sophisticated data monitoring that make it possible to trace back misfunctioning both in the Merger and in other parts of SVT. Furthermore, the Merger has special modes of operation that can be selected for test and diagnostic purposes. In these working modes, the Merger is a powerful tool that allows one to test other SVT boards at their maximum operating frequency.IEEE Transactions on Nuclear Science 09/2002; · 1.45 Impact Factor -
Article: Performance of the CDF online silicon vertex tracker
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ABSTRACT: The online silicon vertex tracker (SVT) is the new trigger processor dedicated to the two-dimensional (2-D) reconstruction of charged particle trajectories at the Level 2 of the Collider Detector at Fermilab (CDF) trigger. The SVT links the digitized pulse heights found within the silicon vertex detector to the tracks reconstructed in the central outer tracker by the Level 1 fast-track finder. Preliminary tests of the system took place during the October 2000 commissioning run of the Tevatron Collider. During the April-October 2001 data taking, it was possible to evaluate the performance of the system. In this paper, we review the tracking algorithms implemented in the SVT and we report on the performance achieved during the early phase of run II.IEEE Transactions on Nuclear Science 07/2002; · 1.45 Impact Factor -
Article: A two-level fanout system for the CDF silicon vertex tracker
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ABSTRACT: The Fanout system is part of the Silicon Vertex Tracker (SVT), a new trigger processor designed to reconstruct charged particle trajectories at level 2 (L2) of the CDF trigger, with a latency of 10 /spl mu/s and an event rate up to 100 kHz. The core of SVT is organized as 12 identical slices, which process in parallel the data from the 12 independent azimuthal wedges of the Silicon Vertex Detector (SVXII). Each SVT slice links the digitized pulse heights found within one SVXII wedge to the tracks reconstructed by the level I (L1) fast track finder (XFT) in the corresponding 30/spl deg/ angular region of the Central Outer Tracker (COT). Since the XFT tracks are transmitted to SVT as a single data stream, their distribution to the proper SVT slices requires dedicated fanout logic. The fanout system has been implemented as a multiboard project running on a common 20 MHz clock. Track fanout is performed in two steps by one "Fanout A" and two "Fanout B" boards. The architecture, design, and implementation of this system are described.IEEE Transactions on Nuclear Science 01/2002; · 1.45 Impact Factor -
Article: The CDF-II Online Silicon Vertex Tracker
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ABSTRACT: The Online Silicon Vertex Tracker is the new CDF-II level 2 trigger processor designed to reconstruct 2-D tracks within the Silicon Vertex Detector with high speed and accuracy. By performing a precise measurement of impact parameters the SVT allows tagging online B events which typically show displaced secondary vertices. Physics simulations show that this will greatly enhance the CDF-II B-physics capability. The SVT has been fully assembled and operational since the beginning of Tevatron RunII in April 2001. In this paper we briefly review the SVT design and physics motivation and then describe its performance during the early phase (April-October 2001) of run II. Comment: Invited talk at the ICALEPCS2001 Conference, Novermber 27-30, 2001, San Jose, California, 5 pages, LaTex, 3 figures12/2001; -
Conference Proceeding: Performance of the CDF online silicon vertex tracker
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ABSTRACT: The Online Silicon Vertex Tracker (SVT) is the new trigger processor dedicated to the 2-D reconstruction of charged particle trajectories at the Level 2 of the CDF trigger. The SVT links the digitized pulse heights found within the Silicon Vertex detector to the tracks reconstructed in the Central Outer Tracker by the Level 1 Fast Track finder. Preliminary tests of the system took place during the October 2000 commissioning run of the Tevatron Collider. During the April-October 2001 data taking SVT was fully assembled and it was possible to obtain clearer and more important results on the performance of the system. In this paper we review the tracking algorithms implemented in the SVT and we report on the performance achieved during the early phase of run II.Nuclear Science Symposium Conference Record, 2001 IEEE; 12/2001 -
Conference Proceeding: THE CDF ONLINE SILICON VERTEX TRACKER
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ABSTRACT: The Silicon Vertex Tracker (SVT) is the new trigger processor which reconstructs 2-D tracks with high speed and accuracy at the level 2 trigger of the CDFII exper-iment. SVT allows tagging events with secondary vertices and therefore enhances the CDFII B-physics capability. SVT has been fully assembled and operational since the beginning of Tevatron RunII in April 2001. In this paper we brieey re-view the SVT design and physics motivation and then describe its performance during the early phase of CDF RunII.7th International Conference on Advanced Technology and Particle Physics (ICATPP 2001), Villa Olmo, Como Italy; 10/2001 -
Article: Error handling for the CDF online silicon vertex tracker
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ABSTRACT: The online silicon vertex tracker (SVT) is composed of 104 VME 9U digital boards (of eight different types). Since the data output from the SVT (few MB/s) are a small fraction of the input data (200 MB/s), it is extremely difficult to track possible internal errors by using only the output stream. For this reason, several diagnostic tools have been implemented: local error registers, error bits propagated through the data streams, and the Spy Buffer system. Data flowing through each input and output stream of every board are continuously copied to memory banks named spy buffers, which act as built-in logic state analyzers hooked continuously to internal data streams. The contents of all buffers can be frozen at any time (e.g., on error detection) to take a snapshot of all data flowing through each SVT board. The spy buffers are coordinated at system level by the Spy Control Board. The architecture, design, and implementation of this system are describedIEEE Transactions on Nuclear Science 09/2001; · 1.45 Impact Factor -
Conference Proceeding: Error handling for the CDF Silicon Vertex Tracker
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ABSTRACT: The SVT online tracker for the CDF upgrade reconstructs two-dimensional tracks using information from the Silicon Vertex detector (SVXII) and the Central Outer Tracker (COT). The SVT has an event rate of 100 kHz and a latency time of 10 μs. The system is composed of 104 VME 9U digital boards (of 8 different types) and it is implemented as a data driven architecture. Each board runs on its own 30 MHz clock. Since the data output from the SVT (few Mbytes/sec) are a small fraction of the input data (200 Mbytes/sec), it is extremely difficult to track possible internal errors by using only the output stream. For this reason several diagnostic tools have been implemented: local error registers, error bits propagated through the data streams and the Spy Buffer system. Data flowing through each input and output stream of every board are continuously copied to memory banks named Spy Buffers which act as built in logic state analyzers hooked continuously to internal data streams. The contents of all buffers can be frozen at any time (e.g. on error detection) to take a snapshot of all data flowing through each SVT board. The Spy Buffers are coordinated at system level by the Spy Control Board. The architecture, design and implementation of this system are describedNuclear Science Symposium Conference Record, 2000 IEEE; 02/2000 -
Conference Proceeding: A two-level fanout system for the CDF silicon vertex tracker
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ABSTRACT: The Fanout system is part of the new trigger processor “Silicon Vertex Tracker” (SVT) dedicated to the reconstruction of charged particle trajectories at the Level 2 of the CDF trigger. The SVT has a maximum event rate of 100 kHz and a latency time of 10 μs. Its core is organised as 12 identical systems (slices) running in parallel almost independently. This implementation of the device derives from the geometry of the Silicon Vertex Detector (SVXII) which is divided in 12 identical wedges along the azimuthal angle. Each SVT slice links the digitized pulse heights found within one SVXII wedge to the tracks reconstructed in the corresponding 30° angular region of the Central Outer Tracker (COT) by the Level 1 Fast Track finder (XFT). Since the COT works as a single entity and the XFT tracks are output on a single data stream, their distribution to the proper SVT slices requires a dedicated Fanout system. This system is a multi-board project running on a common 20 MHz clock, where the fanout function is performed in two steps by one “Fanout A” and two “Fanout B” boards. The architecture, design and implementation of this system are describedNuclear Science Symposium Conference Record, 2000 IEEE; 02/2000 -
Conference Proceeding: The SVT hit buffer
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ABSTRACT: The Hit Buffer is part of the Silicon Vertex Tracker, a trigger processor dedicated to the reconstruction of particle trajectories in the Silicon Vertex Detector and the Central Tracking Chamber of the Collider Detector at Fermilab. The Hit Buffer is a high speed data-traffic node, where thousands of words are received in arbitrary order and simultaneously organised in an internal structured data base, to be later promptly retrieved and delivered in response to specific requests. The Hit Buffer is capable to process data at a rate of 25 MHz, thanks to the use of special fast devices like Cache-Tag RAMs and high performance erasable programmable logic devices from the XILINX XC7300 familyNuclear Science Symposium and Medical Imaging Conference Record, 1995., 1995 IEEE; 11/1995 -
Conference Proceeding: The CDF trigger Silicon Vertex Tracker (SVT)
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ABSTRACT: The design is presented for a device presently being built to perform on line track finding and reconstruction for the CDF (Collider Detector at Fermilab) Silicon Vertex Detector (120 k channels). This device will provide track impact parameter information for the CDF Level 2 trigger decision, thus allowing CDF to trigger on events containing a long lived particle, in particular a b-quark. It will be the first device with such a capability installed at a proton-antiproton collider. The capability to separate b decays early in the trigger process is vital to the CDF program to collect a high statistic b sample to attack the study of CP violation in the b sector. Moreover SVT will open access to non-leptonic b decays like B→ππNuclear Science Symposium and Medical Imaging Conference, 1994., 1994 IEEE Conference Record; -
Article: The CDF Silicon Vertex Trigger
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ABSTRACT: The Collider Detector at Fermilab (CDF) experiment's Silicon Vertex Trigger (SVT) is a system of 150 custom 9U VME boards that reconstructs axial tracks in the CDF silicon strip detector in a pipeline. SVT's impact parameter resolution enables CDF's Level 2 trigger to distinguish primary and secondary particles, and hence to collect large samples of hadronic bottom and charm decays. We review some of SVT's key design features. Speed is achieved with custom VLSI pattern recognition, linearized track fitting, pipelining, and parallel processing. Testing and reliability are aided by built-in logic state analysis and test-data sourcing at each board's input and output, a common interboard data link, and a universal “Merger” board for data fan-in/fan-out. Speed and adaptability are enhanced by use of modern FPGAs.Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment. -
Article: Initial experience with the CDF SVT trigger
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ABSTRACT: The Collider Detector at Fermilab (CDF) Silicon Vertex Tracker (SVT) is a device that works inside the CDF Level 2 trigger to find and fit tracks in real time using the central silicon vertex detector information. SVT starts from tracks found by the Level 1 central chamber fast trigger and adds the silicon information to compute transverse track parameters with offline quality in about . The CDF SVT is fully installed and functional and has been exercised with real data during the spring and summer 2001. It is a complex digital device of more than 100 VME boards that performs a dramatic data reduction (only about one event in a thousand is accepted by the trigger). Diagnosing rare failures poses a special challenge and SVT internal data flow is monitored by dedicated hardware and software. This paper briefly covers the SVT architecture and design and reports on the SVT building/commissioning experience (hardware and software) and on the first results from the initial running.Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment.
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Institutions
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2001–2002
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University of Chicago
- Enrico Fermi Institute
Chicago, IL, USA
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