A. Voicila

Université de Cergy-Pontoise, 95001 CEDEX, Ile-de-France, France

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Publications (8)1.75 Total impact

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    ABSTRACT: In this paper, we propose a new implementation of the Extended Min-Sum (EMS) decoder for non-binary LDPC codes. A particularity of the new algorithm is that it takes into accounts the memory problem of the non-binary LDPC decoders, together with a significant complexity reduction per decoding iteration. The key feature of our decoder is to truncate the vector messages of the decoder to a limited number n<sub>m</sub> of values in order to reduce the memory requirements. Using the truncated messages, we propose an efficient implementation of the EMS decoder which reduces the order of complexity to ¿(n<sub>m</sub> log<sub>2</sub> n<sub>m</sub>). This complexity starts to be reasonable enough to compete with binary decoders. The performance of the low complexity algorithm with proper compensation is quite good with respect to the important complexity reduction, which is shown both with a simulated density evolution approach and actual simulations.
    IEEE Transactions on Communications 06/2010; · 1.75 Impact Factor
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    ABSTRACT: In this paper, we propose and study a new family of error-correcting codes. These achieve excellent error performance under an iterative decoding over the binary-input noisy channel and solves the memory space requirements problem of the non-binary LDPC decoders. We named this class of codes, Split non-binary LDPC codes. The main particularity of this new family of codes is that the variable and the check nodes are not defined over the same finite field GF(2<sup>p</sup>), like in the case of classical non-binary LDPC codes. The class of Split non-binary LDPC codes is obviously larger than that of existing types of codes, which gives more degrees of freedom to find good codes when the existing codes show their limits. We provide two examples of interesting split NB-LDPC codes.
    Information Theory, 2008. ISIT 2008. IEEE International Symposium on; 08/2008
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    ABSTRACT: In this paper, we propose a hardware implementation of the EMS decoding algorithm for non-binary LDPC (NB- LDPC) codes, presented in [4]. To the knowledge of the authors this is the first implementation of an GF(q) LDPC decoder for high order fields (q ges 64). The originality of the proposed architecture is that it takes into account the memory problem of the NB-LDPC decoders, together with a significant complexity reduction per decoding iteration which becomes independent from the field's order. The error decoding performance of the low complexity algorithm with proper compensation has been obtained through computer simulations. The frame error rate results are quite good with respect to the important complexity reduction. The results prove also that an implementation of a NB-LDPC decoder is now feasible and the extra complexity of the decoder is balanced by the superior performance of this class of codes. With their foreseen simple architectures and good-error correcting performances, NB-LDPC codes provides a promising vehicle for real-life efficient coding system implementations.
    Consumer Electronics, 2008. ICCE 2008. Digest of Technical Papers. International Conference on; 02/2008
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    ABSTRACT: In this paper, we propose a hardware implementation of the EMS decoding algorithm for non-binary LDPC codes, presented in [10]. To the knowledge of the authors this is the first implementation of a GF(q) LDPC decoder for high order fields (q ges 64). The originality of the proposed architecture is that it takes into account the memory problem of the non-binary LDPC decoders, together with a significant complexity reduction per decoding iteration which becomes independent from the field order. We present the estimation of the non-binary decoder implementation and key metrics including throughput and hardware complexity. The error decoding performance of the low complexity algorithm with proper compensation has been obtained through computer simulations. The frame error rate results are quite good with respect to the important complexity reduction. The results show also that an implementation of a non-binary LDPC decoder is now feasible and the extra complexity of the decoder is balanced by the superior performance of this class of codes. With their foreseen simple architectures and good-error correcting performances, non-binary LDPC codes provide a promising vehicle for real-life efficient coding system implementations.
    Communications and Information Technologies, 2007. ISCIT '07. International Symposium on; 11/2007
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    ABSTRACT: In this paper, we propose a new implementation of the EMS decoder for non binary LDPC codes presented in (D. Declencq and M. Fossorier, 2007). A particularity of the new algorithm is that it takes into accounts the memory problem of the non binary LDPC decoders, together with a significant complexity reduction per decoding iteration. The key feature of our decoder is to truncate the vector messages of the decoder to a limited number nm of values in order to reduce the memory requirements. Using the truncated messages, we propose an efficient implementation of the EMS decoder which reduces the order of complexity to O(n<sub>m</sub> log<sub>2</sub> n<sub>m</sub>), which starts to be reasonable enough to compete with binary decoders. The performance of the low complexity algorithm with proper compensation are quite good with respect to the important complexity reduction, which is shown both with a simulated density evolution approach and actual FER simulations.
    Communications, 2007. ICC '07. IEEE International Conference on; 07/2007
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    ABSTRACT: Dans cet article, nous présentons un algorithme de décodage simplifié des codes LDPC non-binaires, appelé EMS. Cet algorithme est une simplification de l'algorithme somme-produit dans le domaine logarithmique, qui permet des gains en termes de complexité, de stabilité numérique et de réduction de l'espace de stockage des messages. Nous proposons également différentes variantes d'implantation de l'algorithme EMS. Les différentes variantes présentées sont comparées par des courbes de performances (FER) et par la complexité. Cet article présente aussi une comparaison intéressante entre l'algorithme de décodage proposé (EMS) et son homologue binaire Min-Sum en termes de performances de décodage et complexité.
    21° Colloque GRETSI, 2007 ; p. 545-548. 01/2007;
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    ABSTRACT: - Dans cet article, nous présentons un algorithme de décodage simplifié des codes LDPC non-binaires, appelé EMS. Cet algorithme est une simplification de l'algorithme somme-produit dans le domaine logarithmique, qui permet des gains en terme de complexité et de stabilité numérique. Nous proposons également différentes variantes d'implantation de l'algorithme EMS. Les différentes variantes présentées sont comparées en termes de courbes de performances (FER) et complexité.
    20° Colloque sur le traitement du signal et des images, 2005 ; p. 910-913. 01/2005;

Publication Stats

111 Citations
1.75 Total Impact Points

Institutions

  • 2007–2010
    • Université de Cergy-Pontoise
      95001 CEDEX, Ile-de-France, France
  • 2005–2008
    • French National Centre for Scientific Research
      Lutetia Parisorum, Île-de-France, France