Aivars J. Lelis

Army Research Laboratory, Aberdeen Proving Ground, Maryland, United States

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Publications (165)107.7 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: We use hybrid-functional density functional theory-based Charge Transition Levels (CTLs) to study the electrical activity of near-interfacial oxygen vacancies located in the oxide side of 4H-Silicon Carbide (4H-SiC) power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). Based on the “amorphousness” of their local atomic environment, oxygen vacancies are shown to introduce their CTLs either within (permanently electrically active) or outside of (electrically inactive) the 4H-SiC bandgap. The “permanently electrically active” centers are likely to cause threshold voltage (Vth ) instability at room temperature. On the other hand, we show that the “electrically inactive” defects could be transformed into various “electrically active” configurations under simultaneous application of negative bias and high temperature stresses. Based on this observation, we present a model for plausible oxygen vacancy defects that could be responsible for the recently observed excessive worsening of Vth instability in 4H-SiC power MOSFETs under high temperature-and-gate bias stress. This model could also explain the recent electrically detected magnetic resonance observations in 4H-SiC MOSFETs.
    Journal of Applied Physics 07/2015; 118(4):044507. DOI:10.1063/1.4927619 · 2.18 Impact Factor
  • Daniel B. Habersat · Neil Goldsman · Aivars J. Lelis ·

    Materials Science Forum 06/2015; 821-823:697-700. DOI:10.4028/
  • Ronald Green · Aivars Lelis · Mooro El · Daniel Habersat ·

    Materials Science Forum 06/2015; 821-823:677-680. DOI:10.4028/
  • M.A. Anders · P.M. Lenahan · A.J. Lelis ·
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    ABSTRACT: The negative bias temperature instability (NBTI) has been investigated for quite some time in Si based MOSFETs. In these MOSFETs, the response has been interpreted in several ways, primarily in terms of the reaction diffusion model and newer model based on the occupation of a near interface oxide hole trap triggering the generation of silicon dielectric interface traps. SiC based MOSFETs have enormous promise for high power and high temperature applications. Consequently, device performance at elevated temperatures of these devices is a topic of great current interest. We have begun a magnetic resonance based study of NBTI in 4H-SiC devices and find, among other things, that elevated temperature and negative gate bias generates structural changes (associated with electrically active defects) within the SiC. These observations strongly suggest that SiC NBTI is significantly different and likely more complex than the NBTI processes taking place in silicon based devices. However, other observations suggest that one aspect of NBTI, the occupation of near-interfacial oxide hole traps called E' centers, takes place in both systems.
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    ABSTRACT: In this paper, an exceptionally sensitive form of electron paramagnetic resonance called electrically detected magnetic resonance (EDMR) is utilized to investigate performance limiting imperfections at and very near the interface of 4H-silicon carbide MOSFETs. EDMR measurements are made over an extremely wide range of frequencies, 16 GHz-350 MHz. Multiple interface/near interface defects are identified and strong evidence for significant disorder at the interface region is presented.
    IEEE Transactions on Electron Devices 02/2015; 62(2):301-308. DOI:10.1109/TED.2014.2364722 · 2.47 Impact Factor
  • Aivars J. Lelis · Ron Green · Daniel B. Habersat · Mooro El ·
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    ABSTRACT: A review of the basic mechanisms affecting the stability of the threshold voltage in response to a bias-temperature stress is presented in terms of the charging and activation of near-interfacial oxide traps. An activation energy of approximately 1.1 eV was calculated based on new experimental results. Implications of these factors, including the recovery of some bias-temperature stress-activated defects, for improved device reliability testing are discussed.
    IEEE Transactions on Electron Devices 02/2015; 62(2):316-323. DOI:10.1109/TED.2014.2356172 · 2.47 Impact Factor
  • A.J. Lelis · R. Green · M. El ·
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    ABSTRACT: With the introduction of SiC power MOSFETs into the commercial market place, it is critically important to determine the reliability of these devices. A number of potential issues need to be addressed, including the stability of the device threshold voltage, and the reliability of both the body diode and the gate oxide. An ideal switch has minimal leakage current in the OFF state and very low resistance in the ON state. But an excess negative shift of the threshold voltage under high-temperature reverse-bias (HTRB) conditions can lead to a critical increase in OFF-state leakage current and potential device failure [1]. In a similar fashion, a large positive shift of the threshold voltage may occur under high-temperature gate-bias (HTGB) conditions, wherein a positive bias-temperature stress is applied. This can lead to a significant increase in the ON-state resistance. This work focuses on the stability of the device threshold voltage when subject to bias-temperature stressing, although the reliability of the body diode will also be discussed in the full paper. The primary defects that contribute to shifts in the threshold voltage are near-interfacial oxide traps [2, 3]. A certain number of defect states become activated during device processing. This can vary depending on the details of the processing steps, or may be a function of device design. Typical instabilities of the threshold voltage at room temperature are about 0.25 V. Much larger threshold-voltage instabilities are observed following bias-temperature gate-bias stressing. This is very likely due to the activation of additional oxide traps, which can then participate in the oxide-trap charging process [3]. Since this activation is a function of time at temperature (and bias), more stressful processing conditions can quicken the onset of significant shifts in the threshold voltage during bias-temperature stressing. (Similarly, stressing at higher temperatures also leads to an earlier onset of significant increases in threshold-voltage instability.) As a result, we have observed a marked difference in the onset of significant increases in threshold-voltage instability between different commercial vendors. This difference in bias-temperature stress time can vary in some cases by two orders of magnitude. Detailed results will be provided in the full paper. References 1. Lelis, et al., Mater. Sci. Forum, vols. 679-680, p. 599 (2011). 2. Lelis, et al., IEEE Trans. Elec. Dev., 55:8, 1835 (2008). 3. Lelis, et al., ECS Transactions, Vols. 41(8), p. 203 (2011).
    2014 ECS and SMEQ Joint International Meeting; 10/2014
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    ABSTRACT: In this report we present results comparing lateral MOSFET properties of devices fabricated on Si-face (0001) and A-face (11-20) 4H-SiC, with nitric oxide passivation anneals. We observe a field-effect mobility of 33 cm2/V.s on p-type 5×1015 doped Si-face. These devices have a peak field-effect mobility which increases with temperature, indicative of a channel mobility limited by coulomb scattering. On 1×1016 p-type A-face SiC, the peak channel mobility is observed to be 80 cm2/V.s, with a negative temperature dependence, indicating that phonon-scattering effects dominate, with a much lower density of shallow acceptor traps. This > 2x higher channel mobility would result in a substantial decrease in on-resistance, hence lower power losses, for 4H-SiC power MOSFETs with voltage ratings below 2 kV. However, MOS C-V and gate leakage measurements indicate very different oxide and interface quality on each SiC face. For example, the Fowler-Nordheim (FN) conduction-band (CB) barrier height for electron tunneling at the SiO2/SiC interface is 2.8 eV on Si-face SiC, while it is 2.5 eV or less on A-face SiC. For the valence-band side, the effective FN barrier height at the valence-band (VB) side of only 1.6 eV on A-face SiC, while the VB barrier height is about 3.1 eV on Si-face SiC. Moreover, C-V of the MOS gate on A-face indicates the presence of a high-density of deep hole traps. It is apparent that oxides on alternative crystal faces, very promising in terms of channel mobility, require further study for complete understanding and control of the interface properties.
    2014 MRS Spring Meeting, San Francisco, CA, USA; 04/2014
  • D. P. Ettisserry · N. Goldsman · A. Lelis ·
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    ABSTRACT: In this paper, we present a methodology for the identification and quantification of defects responsible for low channel mobility in 4H-Silicon Carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs). To achieve this, we use an algorithm based on 2D-device simulations of a power MOSFET, density functional simulations, and measurement data. Using physical modeling of carrier mobility and interface traps, we reproduce the experimental I-V characteristics of a 4H-SiC doubly implanted MOSFET through drift-diffusion simulation. We extract the position of Fermi level and the occupied trap density as a function of applied bias and temperature. Using these inputs, our algorithm estimates the number of possible trap types, their energy levels, and concentrations at 4H-SiC/SiO2 interface. Subsequently, we use density functional theory (DFT)-based ab initio simulations to identify the atomic make-up of defects causing these trap levels. We study silicon vacancy and carbon di-interstitial defects in the SiC side of the interface. Our algorithm indicates that the Dit spectrum near the conduction band edge (3.25 eV) is composed of three trap types located at 2.8-2.85 eV, 3.05 eV, and 3.1-3.2 eV, and also calculates their densities. Based on DFT simulations, this work attributes the trap levels very close to the conduction band edge to the C di-interstitial defect.
    Journal of Applied Physics 02/2014; 115(10). DOI:10.1063/1.4868579 · 2.18 Impact Factor
  • Ronald Green · Aivars Lelis · Damian Urciuoli · Marc Litz · James Carroll ·
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    ABSTRACT: Commercial SiC MOSFETs were exposed to ionizing radiation to characterize the radiation response and to compare the observed threshold voltage (VT) instability post-radiation exposure, with the VT instability following bias temperature stress (BTS) testing. As expected, a large number of positively charged oxide traps were present in these devices following irradiation, resulting in a significant negative VT shift. However, the observed VT instability following irradiation was much smaller than that for similarly processed devices exposed to a BTS. Irradiated devices subjected to unbiased thermal treatments experienced a significant annealing of trapped holes above 100 °C. However, isochronal annealing treatments did not significantly alter the number of switching oxide traps, suggesting that a large portion of the traps activated by irradiation may lie deeper within the SiO2, beyond the tunneling distance from the SiC.
    Materials Science Forum 02/2014; 778-780:533-536. DOI:10.4028/
  • A. Lelis · D. Habersat · R. Green · E. Mooro ·
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    ABSTRACT: A brief review of the key results and issues regarding the threshold-voltage instability effect in SiC MOSFETs is presented. These include the basic effect, the strong dependence on measurement conditions, the effect of high-temperature bias stressing, and the implications for reliability testing.
    224th ECS Meeting; 10/2013
  • P.M. Lenahan · C.J. Cochrane · A. Lelis ·

    224th ECS Meeting; 10/2013
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    ABSTRACT: We observe an unusual instability in the SiC DMOSFET transistor characteristics. From a series of bias conditions at elevated temperatures, we conclude that a high density of hole traps in the oxide near the SiO2/SiC interface are responsible.
    2013 IEEE International Integrated Reliability Workshop (IIRW); 10/2013
  • C. J. Cochrane · P. M. Lenahan · A. J. Lelis ·
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    ABSTRACT: We use three electrically detected magnetic resonance (EDMR) approaches to explore nitric oxide (NO) annealing in 4H SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). One approach is sensitive to defects at the interface and those extending into the SiC. Two of these approaches are particularly sensitive to SiC/SiO2 interface defects. They show that NO anneals decrease the EDMR response. Since this and earlier studies indicate the ubiquitous presence of silicon vacancy centers in SiC MOSFETs, our results provide strong circumstantial evidence that these defects play an important role in limiting device performance and that NO anneals are effective in reducing their populations.
    Applied Physics Letters 05/2013; 102(19). DOI:10.1063/1.4805355 · 3.30 Impact Factor
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    ABSTRACT: In this paper, we report our recently developed 2nd Generation, large-area (56 mm2 with an active conducting area of 40 mm2) 4H-SiC DMOSFET, which can reliably block 1600 V with very low leakage current under a gate-bias (VG) of 0 V at temperatures up to 200°C. The device also exhibits a low on-resistance (RON) of 12.4 mΩ at 150 A and VG of 20 V. DC and dynamic switching characteristics of the SiC DMOSFET have also been compared with a commercially available 1200 V/ 200 A rated Si trench gate IGBT. The switching energy of the SiC DMOSFET at 600 V input voltage bus is > 4X lower than that of the Si IGBT at room-temperature and > 7X lower at 150°C. A comprehensive study on intrinsic reliability of this 2nd generation SiC MOSFET has been performed to build consumer confidence and to achieve broad market adoption of this disruptive power switch technology.
    Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on; 05/2013
  • Source
    A. Lelis · R. Green · M. El · D. Habersat ·
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    ABSTRACT: A review of the threshold-voltage instability effect in SiC MOSFETs and the issues regarding the effect of stress and measurement conditions in determining the reliability of these devices is presented. The complex response of near-interfacial oxide traps, as well as other interfacial charge, to bias and temperature with time is discussed, and how it affects the accuracy of reliability measurements. The strong dependence on measurement speed is also addressed. All these issues point to the need for a separate, appropriate reliability test standard for SiC MOSFETs, rather than using the existing standard based on Si technology.
    ECS Transactions 03/2013; 50(3):251-256. DOI:10.1149/05003.0251ecst
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    ABSTRACT: The 4H-SiC/SiO2 interface in MOSFET devices contains a high density of electrically active traps. Recent work has revealed an inverse relationship between the SiC-SiO2 transition layer width and FET channel mobility. Interfacial N and P, introduced by nitric oxide (NO) anneals, nitrogen plasma (N2P), or phosphosilicate glass (PSG) passivations improve carrier mobility, but a relationship to transition layer width is lacking. We present a characterization of the SiC/SiO2 transition layer as a function of NO anneal time using high resolution transmission electron microscopy (HRTEM), high-angle annular dark-field scanning TEM (HAADF-STEM), and electron energy-loss spectroscopy (EELS). The transition layer was measured with HRTEM and HAADF-STEM and characterized by the evolution of the C/Si and O/Si composition ratios and the Si-L2,3 edge in the EEL spectra across the interface. We show an inverse relationship of NO anneal time and transition layer width, which correlates with improved channel mobility, increased N interfacial density, and reduced interface trap density. No excess C was noted at the interface. NO annealed samples are compared to N2P and PSG passivations.
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    ABSTRACT: The 4H-SiC(0001)/SiO2 interface has a variety of likely defects as reported in the literature. We investigate the defects at the SiC side of the interface using density functional theory. We also investigate the effects of passivating these states. The defects studied include a single carbon interstitial, a carbon pair interstitial, and a silicon vacancy at the interface. Density functional theory has been employed to calculate the total and projected density of states (pDOS) and the energy levels of the defects. The results of our calculations indicate that a carbon interstitial and a pair of carbons give rise to traps near the conduction band and valence band. The silicon vacancy gives rise to traps that are closer to the valence band. The effects of hydrogen and nitrogen passivation on the defect energy levels have been investigated. Our studies indicate that hydrogen and nitrogen passivation can eliminate states near the conduction and valence bands, although in some cases they may introduce levels in the midgap.
    Journal of Applied Physics 02/2013; 113(5). DOI:10.1063/1.4789615 · 2.18 Impact Factor
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    ABSTRACT: We present a systematic characterization of the transition layer at the 4H-SiC/SiO2 interface as a function of nitric oxide (NO) post-annealing time, using high-resolution transmission electron microscopy for structural characterization and spatially resolved electron energy-loss spectroscopy for chemical analysis. We propose a systematic method for determining transition layer width by measuring the monotonic chemical shift of the Si-L2,3 edge across the interface, and compare its efficacy to traditional measures from the literature, revealing the proposed method to be most reliable. A gradual shift in the Si-L2,3 edge onset energy suggests mixed Si-C/Si-O bonding in the transition layer. We confirm an inverse relationship between NO-anneal time and transition layer width, which correlates with improved channel mobility, enhanced N density at the interface, and decreased interface trap density. No excess C was noted in the interfacial region.
    Journal of Applied Physics 01/2013; 113(4):044517. DOI:10.1063/1.4789924 · 2.18 Impact Factor
  • D.B. Habersat · A.J. Lelis · N. Goldsman ·
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    ABSTRACT: A time domain, drift-diffusion based numerical simulator has been developed to better understand the influence of mobile ion transport in gate oxides for SiC power MOSFETs. Experimental evidence of mobile ion contamination in SiC MOS has been well documented in general, but proper analysis has been hampered by the presence of significant numbers of defects that distort the results. We report here on the initial results from a numerical simulator that will be able to incorporate models for these additional defect mechanisms in order to provide insight on these key mechanisms that are limiting the performance and reliability of SiC MOS technologies.
    Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on; 01/2013

Publication Stats

2k Citations
107.70 Total Impact Points


  • 1993-2015
    • Army Research Laboratory
      Aberdeen Proving Ground, Maryland, United States
  • 2006
    • Tel Aviv University
      • School of Electrical Engineering
      Tell Afif, Tel Aviv, Israel
  • 2005
    • University of Maryland, College Park
      • Department of Electrical & Computer Engineering
      CGS, Maryland, United States
  • 2001
    • Loyola University Maryland
      Baltimore, Maryland, United States
  • 1996
    • Pennsylvania State University
      • Department of Engineering Science and Mechanics
      University Park, MD, United States