A. Lelis

Northrop Grumman, Falls Church, Virginia, United States

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Publications (133)99.47 Total impact

  • 2014 MRS Spring Meeting, San Francisco, CA, USA; 04/2014
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    ABSTRACT: In this paper, we present a methodology for the identification and quantification of defects responsible for low channel mobility in 4H-Silicon Carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs). To achieve this, we use an algorithm based on 2D-device simulations of a power MOSFET, density functional simulations, and measurement data. Using physical modeling of carrier mobility and interface traps, we reproduce the experimental I-V characteristics of a 4H-SiC doubly implanted MOSFET through drift-diffusion simulation. We extract the position of Fermi level and the occupied trap density as a function of applied bias and temperature. Using these inputs, our algorithm estimates the number of possible trap types, their energy levels, and concentrations at 4H-SiC/SiO2 interface. Subsequently, we use density functional theory (DFT)-based ab initio simulations to identify the atomic make-up of defects causing these trap levels. We study silicon vacancy and carbon di-interstitial defects in the SiC side of the interface. Our algorithm indicates that the Dit spectrum near the conduction band edge (3.25 eV) is composed of three trap types located at 2.8-2.85 eV, 3.05 eV, and 3.1-3.2 eV, and also calculates their densities. Based on DFT simulations, this work attributes the trap levels very close to the conduction band edge to the C di-interstitial defect.
    Journal of Applied Physics 02/2014; 115(10). · 2.21 Impact Factor
  • 224th ECS Meeting; 10/2013
  • 224th ECS Meeting; 10/2013
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    ABSTRACT: We use three electrically detected magnetic resonance (EDMR) approaches to explore nitric oxide (NO) annealing in 4H SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). One approach is sensitive to defects at the interface and those extending into the SiC. Two of these approaches are particularly sensitive to SiC/SiO2 interface defects. They show that NO anneals decrease the EDMR response. Since this and earlier studies indicate the ubiquitous presence of silicon vacancy centers in SiC MOSFETs, our results provide strong circumstantial evidence that these defects play an important role in limiting device performance and that NO anneals are effective in reducing their populations.
    Applied Physics Letters 05/2013; 102(19). · 3.52 Impact Factor
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    ABSTRACT: The 4H-SiC/SiO2 interface in MOSFET devices contains a high density of electrically active traps. Recent work has revealed an inverse relationship between the SiC-SiO2 transition layer width and FET channel mobility. Interfacial N and P, introduced by nitric oxide (NO) anneals, nitrogen plasma (N2P), or phosphosilicate glass (PSG) passivations improve carrier mobility, but a relationship to transition layer width is lacking. We present a characterization of the SiC/SiO2 transition layer as a function of NO anneal time using high resolution transmission electron microscopy (HRTEM), high-angle annular dark-field scanning TEM (HAADF-STEM), and electron energy-loss spectroscopy (EELS). The transition layer was measured with HRTEM and HAADF-STEM and characterized by the evolution of the C/Si and O/Si composition ratios and the Si-L2,3 edge in the EEL spectra across the interface. We show an inverse relationship of NO anneal time and transition layer width, which correlates with improved channel mobility, increased N interfacial density, and reduced interface trap density. No excess C was noted at the interface. NO annealed samples are compared to N2P and PSG passivations.
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    ABSTRACT: The 4H-SiC(0001)/SiO2 interface has a variety of likely defects as reported in the literature. We investigate the defects at the SiC side of the interface using density functional theory. We also investigate the effects of passivating these states. The defects studied include a single carbon interstitial, a carbon pair interstitial, and a silicon vacancy at the interface. Density functional theory has been employed to calculate the total and projected density of states (pDOS) and the energy levels of the defects. The results of our calculations indicate that a carbon interstitial and a pair of carbons give rise to traps near the conduction band and valence band. The silicon vacancy gives rise to traps that are closer to the valence band. The effects of hydrogen and nitrogen passivation on the defect energy levels have been investigated. Our studies indicate that hydrogen and nitrogen passivation can eliminate states near the conduction and valence bands, although in some cases they may introduce levels in the midgap.
    Journal of Applied Physics 02/2013; 113(5). · 2.21 Impact Factor
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    ABSTRACT: We present a systematic characterization of the transition layer at the 4H-SiC/SiO2 interface as a function of nitric oxide (NO) post-annealing time, using high-resolution transmission electron microscopy for structural characterization and spatially resolved electron energy-loss spectroscopy for chemical analysis. We propose a systematic method for determining transition layer width by measuring the monotonic chemical shift of the Si-L2,3 edge across the interface, and compare its efficacy to traditional measures from the literature, revealing the proposed method to be most reliable. A gradual shift in the Si-L2,3 edge onset energy suggests mixed Si-C/Si-O bonding in the transition layer. We confirm an inverse relationship between NO-anneal time and transition layer width, which correlates with improved channel mobility, enhanced N density at the interface, and decreased interface trap density. No excess C was noted in the interfacial region.
    Journal of Applied Physics 01/2013; 113(4):044517. · 2.21 Impact Factor
  • D.B. Habersat, A.J. Lelis, N. Goldsman
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    ABSTRACT: A time domain, drift-diffusion based numerical simulator has been developed to better understand the influence of mobile ion transport in gate oxides for SiC power MOSFETs. Experimental evidence of mobile ion contamination in SiC MOS has been well documented in general, but proper analysis has been hampered by the presence of significant numbers of defects that distort the results. We report here on the initial results from a numerical simulator that will be able to incorporate models for these additional defect mechanisms in order to provide insight on these key mechanisms that are limiting the performance and reliability of SiC MOS technologies.
    Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on; 01/2013
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    ABSTRACT: In this work, we use Density Functional Theory (DFT)-based electronic structure calculations, together with 2D-Device simulations and experiments, to identify and quantify mobility-limiting defects at the 4H-Silicon Carbide (0001) / Silicon Dioxide interface of a Silicon Carbide (SiC) DMOSFET channel. DFT simulations are performed on a variety of possible interfacial defects including the single Carbon interstitial and the Carbon dimer interstitial to calculate their projected Density of States (pDOS) and energy levels. A unique methodology is presented to determine the defect energy levels and corresponding defect concentrations along the channel using DFT calculations, 2D-Device simulations and device I-V measurements. By comparing the results obtained from DFT and 2D-Device simulations, we identified single Carbon interstitials to be the main contributor to mobility-limiting near-interface traps. The defect concentration was also calculated for various locations in the channel.
    Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on; 01/2013
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    ABSTRACT: The potential presence of a transition layer at the SiC/SiO2 interface may affect the electronic characteristics of SiC devices. Several experiments indicate the presence of C-O-Si bridges [1-3] at the interface. We investigated and compared the effect of possible interface structures on the total, and projected density, of states of the SiC/SiO2 system with the use of density functional theory (DFT). We also utilized the Monte Carlo carrier transport modeling technique to obtain the average velocities and mobilities of each structure. The ionized impurity limited mobility of likely structures has been calculated. We constructed various structures with the forms of SiOxCy, and Si1-xCxO2 in both SiC, and SiO2 sides of the interface. According to our calculations, strong possible candidates for generating the traps near the conduction band are SiOxCy structures formed by replacing carbon atoms in SiC with oxygen. The overall mobility, and the ionized impurity limited mobility decrease as the number of O(C) in the SiC side of the SiOxCy structures increase. Moreover, the calculated ionized impurity limited mobility is less than 30 cm2/Vs in low external field.
    Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on; 01/2013
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    ABSTRACT: In this paper, we report our recently developed 2nd Generation, large-area (56 mm2 with an active conducting area of 40 mm2) 4H-SiC DMOSFET, which can reliably block 1600 V with very low leakage current under a gate-bias (VG) of 0 V at temperatures up to 200°C. The device also exhibits a low on-resistance (RON) of 12.4 mΩ at 150 A and VG of 20 V. DC and dynamic switching characteristics of the SiC DMOSFET have also been compared with a commercially available 1200 V/ 200 A rated Si trench gate IGBT. The switching energy of the SiC DMOSFET at 600 V input voltage bus is > 4X lower than that of the Si IGBT at room-temperature and > 7X lower at 150°C. A comprehensive study on intrinsic reliability of this 2nd generation SiC MOSFET has been performed to build consumer confidence and to achieve broad market adoption of this disruptive power switch technology.
    Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on; 01/2013
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    ABSTRACT: A spin dependent recombination (SDR) spectrum observed in a wide range of SiC metal oxide semiconducting field effect transistors (MOSFETs) has previously been only tentatively linked to a silicon vacancy or vacancy related defect. By resolving hyperfine interactions in SDR detected spectra with 13C nuclei, we provide an extremely strong argument identifying the SDR spectrum with a silicon vacancy. Since the silicon vacancy spectrum dominates the SDR response in a wide variety of SiC MOSFETs, silicon vacancies are quite important traps in this technology.
    Applied Physics Letters 01/2012; 100(2). · 3.52 Impact Factor
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    ABSTRACT: Electron–hole-recombination-induced stacking faults (SFs) have been shown to degrade the electrical characteristics of SiC power pin and MPS diodes and DMOSFETs with thick drift epitaxial layers. In this letter, we investigate the effects of bipolar current stress on the electrical characteristics of ion-implanted gate vertical-channel JFETs with 100-$\mu \hbox{m}$ drift epilayers. JFETs are stressed at a fixed gate–drain dc bipolar current density of 100 $\hbox{A/cm}^{2}$ for 5 h. Several JFETs exhibit severe forward gate–drain voltage degradation, while others show intermediate or no degradation. As degradation under bipolar current stress is caused by basal plane dislocation (BPD)-induced SF formation and expansion, the differences in degradation severity are attributed to the nonuniform BPD concentrations in the JFETs' drift epitaxial layers. Forward/reverse gate–source, transfer, reverse gate–drain, and blocking voltage JFET characteristics exhibit no degradation with bipolar stress. Forward gate–drain voltage and on-state conduction degrade in affected JFETs. The degradations are fully reversed by annealing at 350 $^{\circ}\hbox{C}$ for 96 h, while nondegraded electrical characteristics remain unaffected by the annealing. These results suggest that elevated-temperature bipolar JFET operation can proceed without BPD-induced SF-related degradation. In the absence of BPDs, bipolar operation does not impact JFET electrical characteristics.
    IEEE Electron Device Letters 01/2012; 33(7):952-954. · 2.79 Impact Factor
  • Materials Science Forum 01/2012; 717-720:1065-1068.
  • Materials Science Forum 01/2012; 717-720:1059-1062.
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    ABSTRACT: We demonstrate a very powerful electrically detected magnetic resonance (EDMR) technique, spin dependent charge pumping (SDCP) and apply it to 4H SiC metal-oxide-semiconductor field-effect-transistors. SDCP combines a widely used electrical characterization tool with the most powerful analytical technique for providing atomic scale structure of point defects in electronic materials. SDCP offers a large improvement in sensitivity over the previously established EDMR technique called spin dependent recombination, offering higher sensitivity and accessing a wider energy range within the bandgap.
    Applied Physics Letters 08/2011; 99(8). · 3.52 Impact Factor
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    ABSTRACT: We have developed a new technique, spin dependent charge (SDCP) pumping which combines the unrivaled analytical power of EPR to identify the atomic scale nature of point defects with charge pumping, a widely used electrical characterization technique used to study interface/near interface defects in MOSFETs. We demonstrate SDCP to be a very powerful tool with potential to be of widespread use to the MOSFET reliability community.
  • Ronald Green, Aivars Lelis, Daniel Habersat
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    ABSTRACT: The application of existing reliability test standards, based on Si technology, to SiC power MOSFET reliability qualification can in some cases result in ambiguous test results. Depending on the exact measurement procedure, a given device stress tested under identical conditions may either pass or fail. The large variations observed in ID-VGS characteristics, and accompanying shift in threshold voltage (VT) and change in leakage current, are likely due to the complex time, temperature, and bias dependent nature of the charging and discharging of significant numbers of near-interfacial oxide traps (and possibly mitigated by the movement of mobile ions) which are not present in Si power devices. The variation in VT following a high temperature gate-bias (HTGB) stress is shown to be dependent on the measurement delay time, sweep direction, and temperature. Negative gate-bias temperature stress results show that device reliability may be limited due to increased drain leakage current in the OFF-state, which is caused by large shifts in VT depending on the gate-bias stress time, bias magnitude, and stress temperature. In addition, positive gate-bias stressing at elevated temperature may increase power dissipation in the ON-state.
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    ABSTRACT: The U.S. Army Research Laboratory is investigating performance and reliability issues associated with the development of n-channel 4H-SiC DMOSFET devices for advanced power conversion systems. The threshold-voltage instability (VT) effect generally observed in state-of-the-art SiC MOSFETs can be explained by an electron tunneling mechanism, where electrons tunnel in and out of near interfacial oxide traps from the underlying SiC substrate [1]. This effect is very similar to that observed in irradiated Si MOSFETs, and described by the Harry Diamond Laboratory (HDL) Hole Trap Model, which attributed that observed instability to the charging and discharging of an oxide trap associated with an oxygen-vacancy defect — the so-called E ′ center [2]. The pre-cursor site for this trap is a weak Si-Si bond which may be broken by the hole-trapping process. It apparently can also be broken by the application of an electric field at elevated temperature. Recent electron spin resonance (ESR) measurements used to study negative bias temperature instability (NBTI) in Si MOS test structures have shown an increase in the number of these E′ defects with the simultaneous application of both a high-temperature and gate-bias stress [3]. This effect may also explain previous high-temperature gate bias (HTGB) stress testing results of power SiC MOSFETs, including the case of self-heating caused by ON-state current stressing, which revealed a significant increase in the VT instability [4]. This result was unexpected since the tunneling process is generally insensitive to changes in temperature. However, since recent ESR results in the literature have identified an E′-type oxide defect in SiC MOS-based devices as well [5], it may very well be that additional oxide traps are also being activated under bias at high temperature in SiC MOSFETs.

Publication Stats

934 Citations
99.47 Total Impact Points


  • 2009–2010
    • Northrop Grumman
      Falls Church, Virginia, United States
  • 2007–2009
    • Tel Aviv University
      • School of Electrical Engineering
      Tel Aviv, Tel Aviv, Israel
    • Loyola University Maryland
      Baltimore, Maryland, United States
  • 2005–2009
    • University of Maryland, College Park
      • Department of Electrical & Computer Engineering
      College Park, MD, United States
  • 1996–2009
    • Pennsylvania State University
      • Department of Engineering Science and Mechanics
      University Park, Maryland, United States
  • 1993–2009
    • Army Research Laboratory
      Aberdeen Proving Ground, Maryland, United States