ABSTRACT: In this paper, we report detailed studies on process challenges and solutions when super-thick gate DECMOS and thin gate CMOS are integrated together in 0deg on-axis <100> substrate. It has been found that large intra-wafer VT variation (sigma ~ 90 mV) and inter-wafer VT offset (~150 mV) are caused by single (f high energy WELL implant and front and back wafer surface swapping. A high energy implant method has been found very effective in reducing the VT variation to a ~30 mV. Low gate oxide breakdown at the thin gate active region edge has been solved by adding super-thick gate oxide buffer region between thin gate oxide and field oxide. Proper integration sequence has been used to minimize dopant ashout.
Semiconductor Manufacturing, 2006. ISSM 2006. IEEE International Symposium on; 10/2006