Yung-Yu Hsu

imec Belgium, Louvain, Flemish, Belgium

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Publications (10)1.48 Total impact

  • Hsien-Chie Cheng · Kun-Yu Hsieh · Yung-Yu Hsu · Ruoh-Huey Uang ·
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    ABSTRACT: This paper aims at developing an effective scheme for design optimization of a novel nanocomposite-typed flip chip (FC) technology, constructed by integrating an Ag-nanowire/polymer nanocomposite film together with a nonconductive paste (NCP) technology. The objective of the optimization problem is to achieve the optimal process-induced thermal-mechanical behaviors of the novel FC technology during the NCP bonding process through the selection of material properties, process parameters and geometry data. The process-induced thermal-mechanical behaviors are evaluated using a process-dependent simulation methodology that integrates both transient thermal and nonlinear contact FE analyses and a “death-birth” meshing scheme. The validity of the process-dependent FE simulation methodology is also confirmed through experiment. To demonstrate the effectiveness of the present design optimization approach, several design problems associated with the FC technology are performed.
    Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009. IMPACT 2009. 4th International; 11/2009
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    ABSTRACT: Extensive understanding and management of the thermal-mechanical characteristics of novel packaging designs during the bonding process are indispensable to the realization of the technologies. Thus, this paper attempts to explore the bonding process-induced thermal-mechanical behaviors of an advanced flip chip (FC) electronic packaging. FC packaging employs a novel anisotropic conductive film, which is a thin composite film composed of polymer matrix and thousands of millions of highly oriented, 1-D silver (Ag) nanowires on the scale of 200 nanometers in diameter. For carrying out the process simulation, a process-dependent finite element (FE) simulation methodology that integrates both thermal and nonlinear contact FE analyses and a special meshing scheme is applied. The material properties of the nanoscale Ag wires are first explored using molecular dynamics (MD) simulations. By the characterized material properties of the Ag nanowires, the effective material properties of the composite film are derived through two theoretical approaches: 1) the rule-of-mixture (ROM) technique and 2) the proposed FE method-based approach. The predicted results by these two approaches are extensively compared with each other to examine the feasibility of using the widely used ROM technique for such cases. In addition, the validity of the proposed process-dependent FE simulation methodology is also confirmed through three experiments: 1) micro-thermocouple measurement of temperature; 2) Twyman-Green Moire interferometry measurement of out-of-plane deformations; and 3) portable engineering Moire interferometry measurement of in-plane deformations. Throughout the investigation, the effectiveness of the novel interconnect technology is demonstrated. Good agreement with the experiments is also obtained. It is found that the technology may ensure good electrical performance and structural integrity, not only at room temperature but even at elevated temperature, based on its substantial c- - ontact stresses but minor peeling stresses on the bonding line, together with a moderate, process-induced warpage on the substrate.
    IEEE Transactions on Advanced Packaging 06/2009; 32(2-32):546 - 563. DOI:10.1109/TADVP.2009.2013725 · 1.28 Impact Factor
  • M.C. Hsieh · Yung-Yu Hsu · Chao-Liang Chang ·
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    ABSTRACT: The topics of 3D-IC packages are now widely studied around the world in recent years, not only in electronic packaging areas, but also in bioengineering areas and so on. With the developments of 3D-ICs technologies, packaging effects on 3D-ICs of Cu/low-k interconnects have become a critical reliability issue, especially in the assembly processes and reliability test procedures. In 3D-IC packages, low-k dielectrics are now popularly used to retard the RC delayed effects, increase the bandwidth, reduce the inductance and decrease the power consumption. By using the weaker low-k dielectrics instead of traditional TEOS interlevel dielectrics, packaging induced interfacial delamination in low-k interconnects has been widely observed that raising serious reliability concerns for Cu/low-k chips. In this paper, the thermal induced stresses of Cu/low-k interconnect in 3D-IC structures during reliability test process are obtained by three-dimensional finite element analysis. The packaging induced crack in Cu/low-k structures is also studied. The results show that the interfacial cracks in 3D-ICs significantly impact the distribution of thermal induced stresses in Cu/low-k structures and could have prominent influence on their reliability
    Microsystems, Packaging, Assembly Conference Taiwan, 2006. IMPACT 2006. International; 11/2006
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    ABSTRACT: As microelectronic packaging industry grows explosively, high I/O density interconnects and reliable packaging design are recognized as the main concern of the IC packaging industry. Hence, in this investigation, a novel type of anisotropic conductive film (ACF) composed of cobalt nanowires and polymer was developed and used in place of conventional solder bumps for ultra-fine pitch interconnect. Unlike some other ACF materials that blend either nanowires, tubes, or powders in polymer, the nanowires entrenched in polymer is well aligned in one direction so as to achieve high anisotropic conductance. Basically, the material properties of the nanowire/polymer-based conductive film would have a great effect on the thermal-mechanical behaviors of the technology, which would generally lead to a reliability issue. Thus, the underlying goal of the study was to characterize the out-of-plane mechanical properties, including reduced modulus and hardness, through a nanoindentation technique. The tip of nanoindentation was 300nm in diameter and measured method was force-control. Results show that the mean value of the reduced-modulus of the film is 14.471GPa at a standard deviation of 2.578GPa. These statistical results were based on 102 data points with high consistency.
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    ABSTRACT: As the prediction that the I/O pitch will decrease from 60 um in 2004 to 20 um beyond 2010 by ITRS roadmap, flip chip interconnection by traditional ACF containing conductive particles with micro-meter size will face more and more challenges. One of many possible solutions is using high aspect-ratio metal posts or flake instead of conductive particles for electrical interconnection between chip and substrate. But this interconnection by metal posts is less reliable compared with elastic conductive particles. Therefore we develop a new type of conductive film composed of nanowires and polymer. Unlike some other composed material by blending nanowires, tubes, powders in polymer, the arrangement of nanowires in polymer is highly ordered in X, Y, and Z direction for anisotropic conductance. In order to achieve high reliability performance of this novel package, the structure design of flip chip package constructed by nanowires/polymer conductive film was evaluated by stress simulation and related D.O.E analysis. In this research, series of finite element models were established based on the D.O.E. (design of experiment) matrix. The four factors including thickness of nanowires/polymer composed film, volume ratio of nanowires in nanowires/polymer composed film, CTE and Young's modulus of polymer were used in this D.O.E. matrix. The full factorial DOE matrix was applied to optimize the response of peeling stress. These results indicated that volume ratio of nanowires was the major factor. The other important factor was film thickness. Besides the above stress analysis, we also demonstrated the production of nanowires/polymer composed film. Now we can obtain the silver nanowires/polyimide composed films with diameter of nanowire about 200nm and maximum film thickness up to 50 um. The X-Y insulation resistance is about 4~6 GOmega and Z-direction resistance including the trace resistance (3mm length) is less than 0.2Omega
    Electronics Packaging Technology Conference, 2004. EPTC 2004. Proceedings of 6th; 01/2005
  • Ren-Jen Lin · Yung-Yu Hsu · Yu-Chih Chen · Syh-Yuh Cheng · R.-H. Uang ·
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    ABSTRACT: First Page of the Article
    Electronic Components and Technology Conference, 2005. Proceedings. 55th; 01/2005
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    ABSTRACT: The micro-inductor is a key component in wireless power transmission micro modules. In this paper, an optimum design for the micro-inductor was studied and related MEMS fabrication techniques were also developed. Commercial electromagnetic property analysis software, ANSOFT, was used to screen the main design factors of the micro-inductor. It was found that the high inductance and high quality factors of the micro-inductor implied high power transmission efficiency for the micro-module’s wireless power transmission. The electrical performance of the micro-inductor was affected by the thermal stress and thermal strain induced in the operational environment of the wireless power transmission micro-module. In order to investigate the reliability of the micro-inductor, commercial stress analysis software, ANSYS, was used to calculate thermal stress and thermal strain. The deformed model of the micro-inductor was then imported into ANSOFT in order to calculate its electrical properties. Glass substrate Pyrex 7740 was used to reduce the substrate loss of the magnetic flux of the micro-inductor. The surface micromachining technique, a kind of MEMS processing, was chosen to fabricate the micro-inductor; the coil of the micro-inductor was electroplated with copper to reduce the series resistance. The minimum line width and line space of the coil were 20 μm and 20 μm respectively. Polyimide (PI) was used for supporting the structure of micro-inductors. The maximum shear stress was 74.09MPa and the maximum warpage was 2.197 μm at a thermal loading of 125°C. For the simulated data, the most suitable areas for 31-turn and 48-turn coils were at an area ratio of 1.27 and 2, respectively. The electrical properties of the inductors changed slightly under thermal loading.
    ASME 2004 International Mechanical Engineering Congress and Exposition; 01/2004
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    ABSTRACT: The technology of contactless energy transfer is emerging for application in implantable medical device. High transfer efficiency and high quality factor are specific design requirements for micro-inductors which are key component of contactless energy transfer micro-modules. Thermal stress analysis and electrical analysis of an inductor are sequentially performed to elucidate the effect of thermal strain on the electrical properties of a micro-inductor. Three dimensional finite element models of an inductor were generated by the commercial stress analysis software, ANSYS, to calculate the thermal stress and thermal strain. The deformed model of the inductor was then imported to the commercial electrical property analysis software, ANSOFT, to calculate changes of the electrical properties, such as the inductance, the quality factor and the electrical resistance. The investigation shows that the thermal stress is concentrated at the four corners of the inductor with SU8 support, and that the inductor without SU8 support is twisted without substrate warpage. The electrical properties of inductors do not change dramatically under thermal loading caused by a temperature change from −40°C to 125°C.
    ASME 2003 International Mechanical Engineering Congress and Exposition; 01/2003
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    ABSTRACT: A novel fabrication process to etch, to passivate, and to release single-crystal silicon structures totally in just only one process by inductively coupled plasma reactive ion etching (ICP-RIE) has been presented in this paper. Several kinds of movable actuators such as relay, comb-drive, and capacitance with thickness of 30 μm have been fabricated successfully to demonstrate this fabrication process. Here, experimental investigations about fabrication parameters to get well profile and suspension structures are performed in a STS ICP-RIE system.
    ASME 2002 International Mechanical Engineering Congress and Exposition; 01/2002
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    ABSTRACT: In ICP-RIE process, there have been many investigations on etching rate. However, only few published reports mentioned the sidewall roughness, which is a critical issue for optical devices. Here, experimental investigations about fabrication parameters in the STS Advanced Silicon Etch (ASE) process for sidewall roughness are performed. In our experiments, the photoresist of AZ1500 is used, and several parameters in the ASE process like over time, ramping time, Ar flow rate, platen power, and etching cycle time have been systematically studied. It is found that sidewall mean roughness can be down to 9.11 nm at etching rate of 2.5 µ m/min. Comparing with other published works at similar sidewall roughness (around 10 nm), our experimental data have the highest etching rate. For the same STS ICP-RIE systems, our data have smallest sidewall roughness, comparing to previous literatures.
    Proceedings of SPIE - The International Society for Optical Engineering 11/2001; 4592. DOI:10.1117/12.449008 · 0.20 Impact Factor

Publication Stats

30 Citations
1.48 Total Impact Points


  • 2009
    • imec Belgium
      Louvain, Flemish, Belgium
    • Feng Chia University
      • Department of Aerospace and Systems Engineering
      臺中市, Taiwan, Taiwan
  • 2005-2006
    • Industrial Technology Research Institute
      Hsin-chu-hsien, Taiwan, Taiwan
  • 2004
    • KIIT University
      Bhubaneswar, Orissa, India
  • 2003
    • Kunshan Industrial Technology Research Institute
      Wu-hsien, Jiangsu Sheng, China
  • 2001
    • National Chiao Tung University
      • Department of Mechanical Engineering
      Hsin-chu-hsien, Taiwan, Taiwan

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