Yoann Guillemenet

Université Paris-Sud 11, Orsay, Île-de-France, France

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Publications (12)0.28 Total impact

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    ABSTRACT: The main objective of this paper is to give an overview of different hybrid MRAM/CMOS cells to use in the context of reconfigurable computing. The way to convert magnetic information into an electrical one is not unique and we propose to compare different kind of hybrid cells. These hybrid cells can be used to define structures as Look-up Table, configuration memory point, Flip-flop and other basic elements needed to define programmable logic. Even if these cells were designed for the TAS (Thermally Assisted Switching) MRAM technology, it is possible to adapt them to more advanced technologies such as STT (Spin Transfer Torque).
    New Circuits and Systems Conference (NEWCAS), 2013 IEEE 11th International; 01/2013
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    ABSTRACT: As the fabrication technology node shrinks down to 90nm or below, high standby power becomes one of the major critical issues for CMOS logic circuits due to the high leakage currents. A number of non-volatile storage technologies such as FRAM, MRAM, PCRAM and RRAM and so on, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy D integration after CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and their potential applications in the future.
    Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011; 01/2011
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    ABSTRACT: As the fabrication technology node shrinks down to 90nm or below, high standby power becomes one of the major critical issues for CMOS high-speed computing circuits (e.g. logic and cache memory) due to the high leakage currents. A number of non-volatile storage technologies such as FeRAM, MRAM, PCRAM and RRAM and so on, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy 3D integration after CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and discuss their potential applications in the future from both the physics and architecture points of view.
    IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011; 01/2011
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    Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings; 01/2011
  • Y. Guillemenet, L. Torres, G. Sassatelli
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    ABSTRACT: This study describes the integration of thermally assisted switching magnetic random access memories (TAS-MRAMs) in field-programmable gate array (FPGA) design. The non-volatility is achieved through the use of magnetic tunnelling junctions (MTJs) in an MRAM cell. A TAS scheme is used to write data in the MTJ device, which helps to reduce power consumption during a write operation in comparison with the conventional writing scheme used in MTJ devices. Furthermore, the non-volatility allows reducing both power consumption and configuration time required at each power-up of the circuit in comparison with classical static random access memory-based FPGAs. An innovative architecture furthermore provides run-time reconfigurable (RTR) support at minimum area overhead. A RTR FPGA element using TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.
    IET Computers & Digital Techniques 06/2010; · 0.28 Impact Factor
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    ABSTRACT: The current SRAM based FPGA, are more and more susceptible to Single Event Upset (SEU) due to Neutron particle interference. The problem is exasperated reducing the CMOS submicronic scale in the manufacturing process, specially for the next generation of SRAM-based FPGAs. Nowadays is common practice for SRAM manufactories to embed fault tolerant mechanisms like Error-Correcting Code schemes in SRAM memory banks for CMOS technology below 90 nm, to mitigate SEU. The present work proposes an approach to improve the reliability of the FPGAs, regarding SEU events at ground level for the future submicronic scale technologies proposing the adoption of Magnetic Random Access Memories (MRAMs) cells into a simple fault-tolerant system for FPGAs manufactured below 65 nm submicronic scale.
    ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 13-15 December 2010, Proceedings; 01/2010
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    Lionel Torres, Yoann Guillemenet, Syed Zahid Ahmed
    Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2010, July 12-15, 2010, Las Vegas Nevada, USA; 01/2010
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    ABSTRACT: The need of non volatility along with the added flexibility of un limited reprogramming like SRAM has lead to the concept of universal memories. MRAM (magnetoresistive random access memory) is one prominent member of them. At present only Flash is providing a limited bridge for that. Flash based FPGAs have several benefits being non volatile but unfortunately also loose many of the features which are only possible with SRAM based FPGAs. MRAMs have potential to bridge this gap. This paper will present a brief survey of our work in this regard for creating the entire eco system of software and hardware tool flows, MRAM layout work at 120 nm, exploration environments to conduct complex experiments especially dynamic reconfiguration and multi context FPGAs. MRAM opens new opportunities for them compared to SRAM and Flash. It will discuss the current status of MRAM in industry and our current and future test chips road maps. Provide several references to industry and our published work for details about MRAMs and eFPGAs, to show why we think MRAM can be very interesting element for FPGAs.
    ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings; 01/2009
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    ABSTRACT: This paper describes the integration of a thermally assisted switching magnetic random access memory (TAS-MRAM) in FPGA design. The non-volatility of the latter is achieved through the use of magnetic tunneling junctions (MTJ) in the MRAM cell. A thermally assisted switching scheme is used to write data in the MTJ device, which helps to reduce power consumption during write operation in comparison to the writing scheme in classical MTJ device. Plus, the non-volatility of such a design should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM based FPGAs. A real time reconfigurable (RTR) micro-FPGA using TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.
    Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on; 10/2008
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    Proceedings of the 2008 International Conference on Genetic and Evolutionary Methods, GEM 2008, July 14-17, 2008, Las Vegas, Nevada, USA; 01/2008
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    Guillemenet Y, Torres L, Sassatelli G, Bruchon N
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    ABSTRACT: This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.
    International Journal of Reconfigurable Computing 01/2008;
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    Y. Guillemenet, L. Torres, G. Sassatelli, N. Bruchon

Publication Stats

32 Citations
123 Downloads
718 Views
0.28 Total Impact Points

Institutions

  • 2011
    • Université Paris-Sud 11
      Orsay, Île-de-France, France
  • 2009–2010
    • Université Montpellier 2 Sciences et Techniques
      Montpelhièr, Languedoc-Roussillon, France
  • 2008
    • Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier (LIRMM)
      Montpelhièr, Languedoc-Roussillon, France