ABSTRACT: This paper describes the design of a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) designed and fabricated using 0.18 mum CMOS process. The ADC operates with a supply voltage from 0.9V to 1.4 V and up to 20 kS/s sampling rate. Using charge-scaling technique and a modified dynamic comparator structure, the ADC consumes only 100 nW at V<sub>dd</sub> = 0.9 V and 1 kS/s sampling rate. The ADC was tested and verified for phonocardiography and heart-rate counting.
Integrated Circuits, 2007. ISIC '07. International Symposium on; 10/2007