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ABSTRACT: A test application method to reduce the test application time in full scan designs is presented. It can be used either during or after the test pattern generation phase so that one or more patterns can be reached from an already scanned pattern using scan reapply or scan shift operations. The presented approach is based on established methods for reachability analysis in sequential verification and a fault grading algorithm to ensure that all targeted faults are covered.
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on; 04/2005