S.M. Harb

University of Florida, Gainesville, Florida, United States

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Publications (11)1.33 Total impact

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    ABSTRACT: This paper focuses on TSV and interconnect signal integrity characterization of 3D IC embedded test structures that measure GTL high speed I/O performance. The three Tiers of a CMOS 3D IC were fabricated by MIT Lincoln Laboratory in a 150nm SOI process bonded together and the test structures were ball-bonded on to a custom FR-4 board designed for matched 50Ω microwave and high speed transient measurements. The comparison between on-chip and FR-4 board measurement results for TSV and interconnect signal integrity characterization will be shown and analyzed using equivalent electrical models. In addition, the paper reports extensive additional on-board measurements including, 1) 3D IC GTL I/O response to varying data patterns, 2) Edge timing comparing GTL signals launched from several 3D IC Tiers simultaneously to the same I/O output, and 3) GTL I/O performance under degraded environmental conditions in the 3D IC such as reduced bias.
    Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd; 01/2012
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    ABSTRACT: In this paper, a low-voltage (sub-1 Volt) resistor-free voltage reference is presented. The complete design was simulated and laid out in AMI 0.5 μm CMOS process. The design provides a temperature coefficient of 12.8 ppm/ C over a temperature range from 25 to 100 °C and occupies an area of 0.037 mm . Circuit description and experimental results of the proposed design are also presented.
    Circuits and Systems (ISCAS), 2011 IEEE International Symposium on; 01/2011
  • International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil; 01/2011
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    ABSTRACT: In this paper, we present an enhanced architecture circuit design for embedded jitter measurement using the Vernier delay method with a single delay locked loop (DLL) structure, which characterizes the jitter in the order of picoseconds. The jitter measurement is realized by two delay chains feeding into the clock and data lines of a series of detector components known as a Vernier delay line (VDL). The matching of various delay elements is adjusted on-the-fly by an enhanced structure of a DLL feedback topology. Thereby, reducing the effect of the intrinsic gate delay variations due to process, voltage, temperature (PVT) changes; a limitation that reflects a major drawback of the VDL structure, and requires a large cost of design layout complexity. The nature of the design topology uses a small silicon area with a scalable jitter analyzer circuitry, which is used to collect the jitter on the data signal. The design nature is synthesizable using the field-programmable gate-array (FPGA) implementation. The proposed design estimates a silicon area of 0.074mm2, and HSPICE simulation results indicate a timing resolution of 25ps in a 0.18μm TSMC CMOS process.
    Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference; 01/2011
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    ABSTRACT: This work focuses on characterizing the performance of the 3D TSVs under high speed transient simulation, which could potentially evaluate and verify the electrical models for these vertical connections. A gunning transceiver logic (GTL) I/O on-chip test IC and a CML/thermal test IC has been designed and sent for fabrication using the 3D FDSOI CMOS technology. The GTL I/O circuits are used to inject different data patterns at different frequencies across different tiers. A control MUX with tri-state buffers and control logic can be used to switch between different I/O GTL drivers at different tiers. The GTL I/O test IC is dedicated to measure the NEXT/FEXT crosstalk between vertical connections by firing high speed signals from different tiers. The data-dependent-jitter (DDJ) will be characterized by observing the eye diagram for a random and different data patterns. CML I/O circuits were designed to characterize high speed differential transmission, especially, the performance of high current buffers in the three tiered-system implementation. Differential signals were used to test the performance of through-silicon vias (TSV) and interconnect as the signals transmit from IC tier-to-tier. In addition, temperature sensors were integrated in order to model the 3D thermal performance as affected by the I/O drivers.
    3D System Integration, 2009. 3DIC 2009. IEEE International Conference on; 10/2009
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    ABSTRACT: A high-speed scalable programmable divide-by-N frequency divider is presented. The divider includes a new proposed state look-ahead parallel counter with a basic conventional D-type Flip-Flop (DFF) circuit. The counter is structured from two modules of 2-bit counter stages separated by DFF buffers, where all are triggered at the edge of the input clock. The reload circuit is a single DFF buffer, while the detecting count circuit is constructed from a two level decoder. The M-bit divider critical path delay, which is independent of technology, is approximated to [3.5 + Log4 (M)] of a unit delay close to a 2-input NAND gate. This results in a measured frequency, which slightly drops to about 6% against the increase of the divider bit size. Furthermore, the divider circuit is attractive for continued technology scaling since the architecture is based on using identical modules of small count of CMOS transistors with only threshold voltage technology limitations. The measure rate of the number of transistors is approximated to a linear increase of about 17% per a two-bit increase of the divider size. The presented 8-bit programmable divide-by-N frequency divider is capable of operating up to 2 GHz for a 1.35 V power supply voltage with a maximum power consumption of 16.78 mW and a maximum frequency divider factor of N=256 using the TSMC 0.15 mum digital CMOS process, and gives a measured area of 95*143 mum<sup>2</sup> with a total count of 508 transistors.
    Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on; 06/2008
  • Shadi M. Harb, Janise McNair
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    ABSTRACT: Due to the randomness and mobility of ad hoc networks, estimating the average number of hops becomes very essential in multi-hop ad hoc networks, which is used as a key metric for performance comparison between multi-hop routing protocols; however, most current research derives the average number of hops based on simulations and empirical results, lacking the theoretical analysis of this essential metric. This paper presents a theoretical study of the expected number of hops between any two random nodes using typical modeling assumptions -an N-node randomly Poisson distributed connected network (i.e. for any two random nodes, they are connected by at least one path). The proposed theoretical analysis studies the relationship between the average number of hop counts and other critical ad hoc network parameters such as transmission range (r 0), node density (ρ), and area (A). At last, simulation results will be given to verify the theoretical analysis.
    Wireless Algorithms, Systems, and Applications, Third International Conference, WASA 2008, Dallas, TX, USA, October 26-28, 2008. Proceedings; 01/2008
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    ABSTRACT: A low-power CAM design using a 12-transistor cell is proposed. The CAM cell is based on the conventional 6T cross- coupled inverters used for storing data with an addition of two NMOS transistors for reading out. In addition, the CAM has another four transistors for mask comparison operation through classical pre-charge operation. The read-out port exploits a pre- charge reading mechanism in order to alleviate the drawback of power consumption generated from sensing amplifiers and all other related synchronization circuits which are structured in every column in the memory. Thus, the read and match features can have concurrent operations. An experimental CAM structure of storage size 64-bit x 128-bit is designed using 0.18- μm CMOS single poly and three layers of metals measuring a cell die area of 24.4375 μm<sup>2</sup> and a total silicon area of 0.269192 mm<sup>2</sup>. The circuit works up to 200 MHz in simulation with total power consumption of 0.016 W at 1.8-V supply voltage
    Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on; 11/2007
  • [Show abstract] [Hide abstract]
    ABSTRACT: A low-power CAM design using a 12-transistor cell is proposed. The CAM cell is based on the conventional 6T cross- coupled inverters used for storing data with an addition of two NMOS transistors for reading out. In addition, the CAM has another four transistors for mask comparison operation through classical pre-charge operation. The read-out port exploits a pre- charge reading mechanism in order to alleviate the drawback of power consumption generated from sensing amplifiers and all other related synchronization circuits which are structured in every column in the memory. Thus, the read and match features can have concurrent operations. An experimental CAM structure of storage size 64-bit x 128-bit is designed using 0.18- μm CMOS single poly and three layers of metals measuring a cell die area of 24.4375 μm2 and a total silicon area of 0.269192 mm2. The circuit works up to 200 MHz in simulation with total power consumption of 0.016 W at 1.8-V supply voltage
    Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on; 01/2007
  • [Show abstract] [Hide abstract]
    ABSTRACT: A low-power content addressable memory (CAM) with read/write and mask match ports is proposed. The CAM cell is based on the conventional 6T cross-coupled inverters used for storing data with an addition of two NMOS transistors for reading out. In addition, the CAM has another four transistors for mask comparison operation through classical pre-charge operation. The read-out port exploits a pre-charge reading mechanism in order to alleviate the drawback of power consumption generated from sensing amplifiers and all other related synchronization circuits which are structured in every column in the memory. Thus, the read and match features can have concurrent operations. An experimental CAM structure of storage size 64-bit x 128-bit is designed using 0.18-μm CMOS single poly and three layers of metals measuring a cell die area of 24.4375 μm2 and a total silicon area of 0.269192 mm2. The circuit works up to 200 MHz in simulation with total power consumption of 0.016 W at 1.8-V supply voltage.
    Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings; 01/2007
  • S. Abdel-hafeez, S. Harb
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    ABSTRACT: A novel high-performance priority encoder design using standard CMOS library cell is proposed. The new encoder design implementation accommodates both high- and low-priority functionalities with scalable design structure through a special prefixing scheme. The prefixing scheme is applied to minimize the entire propagation delay and exploit the shared hardware between the high- and low-priority evaluation logics circuitry. The proposed encoder shows significant improvement in terms of speed, robustness for top-level floor plan routing, and modularity with pattern structure in compared to the existing encoder designs. Simulation results are conducted for different encoder inputs through 0.15-mum TSMC CMOS technology, where 32-bit priority encoder is used as a test vehicle for comparison improvement measurements. The expected results show that the 32-bit encoder is operating at a maximum of 667-MHz operating frequency with total count of 1106 transistors and a maximum power consumption of total 13.8 mW
    Circuits and Systems II: Express Briefs, IEEE Transactions on 09/2006; · 1.33 Impact Factor

Publication Stats

13 Citations
1.33 Total Impact Points

Institutions

  • 2007–2008
    • University of Florida
      • Department of Electrical and Computer Engineering
      Gainesville, Florida, United States
  • 2006–2008
    • Jordan University of Science and Technology
      • Department of Computer Engineering
      Irbid, Irbid, Jordan