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ABSTRACT: We present the fabrication process of a fully functional 0.274μm2 6T-SRAM cell with inserted-Ta<sub>x</sub>N<sub>y</sub> tall tripple gate devices. Several advancements over our previous report by A. Naekaerts et al. (2004) are: reduction of the 6T-SRAM cell size from 0.314 to 0.274μm2 using further litho process optimizations; insertion of 5nm TaN-based layer in the gate stack of the cell devices; improved OPC for CD control and integration of SRAM and logic. A high static noise margin of 216mV at 1.0V has been achieved with devices having a Lg=37nm. This is the smallest 6T-SRAM cell with MG devices reported so far.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005