S. P. Oei

University of Cambridge, Cambridge, ENG, United Kingdom

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Publications (4)4.94 Total impact

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    ABSTRACT: This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.
    Journal of Nanoscience and Nanotechnology 12/2008; 8(11):5667-72. · 1.15 Impact Factor
  • Materials Research Society Symposium Proceedings; 01/2007
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    ABSTRACT: Arrays of silicon nanostructures on n- and p-type silicon (100) substrates were fabricated using electron beam annealing of untreated silicon at 1100°C. Following annealing for 15s, the nanostructures exhibit an average height of 8±1nm and a surface density of 11μm−2, independent of the substrate conduction type. Following annealing for 600s the individual nanostructures coalesce and the surface appears roughened with an rms roughness of 30nm. The field emission properties of these nanostructure arrays have been assessed and electron emission through Fowler–Nordheim tunnelling was confirmed. The difference in threshold field for electron emission from the nanostructured and roughened substrates is related to the geometrical differences between the substrate surfaces. At large electric fields, space charge limited conduction dominates the field emission characteristics of the nanostructured surface.
    Current Applied Physics - CURR APPL PHYS. 01/2006; 6(3):503-506.
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    ABSTRACT: This letter considers field emission from self-assembled silicon nanostructure arrays fabricated on n- and p-type silicon (100) substrates using electron beam rapid thermal annealing. Arrays of nanostructures with an average height of 8 nm were formed by substrate annealing at 1100 °C for 15 s. Following conditioning, the Si nanostructure field emission characteristics become stable and reproducible with Fowler–Nordheim tunneling occurring for fields as low as 2 V μm−1. At higher fields, current saturation effects are observed for both n-type and p-type samples. These studies suggest that the mechanism influencing current saturation at high fields acts independently of substrate conduction type.
    Applied Physics Letters 10/2004; 85(15):3277-3279. · 3.79 Impact Factor