T. Uhlig,
A. Bemmann,
C. Ellmers,
F. Furnhammer,
M. Gross,
Y.H. Hu,
J. Liu, R.-R. Ludwig,
M. Reinhold,
M. Stoisiek,
E. Votintseva,
M. Wittmaack
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ABSTRACT: A new smart power SOC IC process including up to 50V HV-MOS transistors, SONOS principle based non-volatile memory components and analog devices using an advanced 0.18μm platform is presented. Process architecture and device portfolio are focused on automotive applications e.g. sensor signal conditioning and integrated output drivers. HV-MOS and SONOS integration as well as device properties are discussed with regard to reliability aspects. Additionally key features of NPN bipolar transistors and depletion NMOST are given.
Power Semiconductor Devices and IC's, 2007. ISPSD '07. 19th International Symposium on; 06/2007
