[show abstract][hide abstract] ABSTRACT: A novel diode-triggered silicon-controlled rectifier (DTSCR) (Mergens et al., 2003) electrostatic discharge (ESD) protection element is introduced for low-voltage application (signal and supply voltages ≤ 1.8 V) with extremely narrow ESD design margins. Trigger-voltage engineering in conjunction with fast and efficient SCR voltage clamping is applied for the protection of ultrasensitive circuit nodes, such as SiGe heterojunction bipolar transistor (HBT) base regions (e.g., f<sub>Tmax</sub>=45 GHz in BiCMOS 0.35-μm LNA input) and thin gate oxides (e.g., t<sub>ox</sub>=1.7 nm in CMOS 0.09-μm high-speed input). Ultrathin gate protection requires a reinforced trigger diode chain to avoid SCR trigger-speed issues resulting in critical trigger-voltage overshoots for very fast ESD transients such as a charged device model (CDM). SCR integration can be realized based on parasitic n-p-n/p-n-p inherent to CMOS devices or can alternatively be implemented based on vertical high-speed SiGe HBT with adjacent p+ SCR anode.
IEEE Transactions on Device and Materials Reliability 10/2005; · 1.52 Impact Factor
[show abstract][hide abstract] ABSTRACT: A novel diode-triggered SCR (DTSCR) ESD protection element is introduced for low-voltage application (signal, supply voltage ≤1.8 V) and extremely narrow ESD design margins. Trigger voltage engineering in conjunction with fast and efficient SCR voltage clamping is applied for the protection of ultra-sensitive circuit nodes, such as SiGe HBT bases (e.g. f<sub>Tmax</sub>=45 GHz in BiCMOS-0.35 μm LNA input) and thin gate-oxides (e.g. tox=1.7 nm in CMOS-0.09 μm input). SCR integration is possible based on CMOS devices or can alternatively be formed by high-speed SiGe HBTs.
[show abstract][hide abstract] ABSTRACT: This paper describes a layout technique to optimize the ESD performance per area for fully silicided NMOS devices by segmenting the active area of drain and source regions. Efficient multi finger triggering is achieved by intrinsic inter-finger-coupling through the bulk enabled by compact finger design. The technique is successfully applied in a 0.13 um and a 0.18 um CMOS technology obtaining HBM ESD capability of up to 8.6 V/um<sup>2</sup>.