Quiyang Li

Seoul National University, Seoul, Seoul, South Korea

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Publications (1)0 Total impact

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    ABSTRACT: Increasingly prominent variational effects impose imminent threat to the progress of VLSI technology. This work explores redundancy, which is a well-known fault tolerance technique, for variation tolerance. It is observed that delay variability can be reduced by making redundant paths distributed or less correlated. Based on this observation, a gate splitting methodology is proposed for achieving distributed redundancy. We show how to avoid short circuit and estimate delay in dual-driver nets which are caused by gate splitting. A spin-off gate placement heuristic is developed to minimize redundancy cost. Monte Carlo simulation results on benchmark circuits show that our method can improve timing yield from 59% to 72% with only 03% increase on cell area and 2.2% increase on wirelength on average.
    Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on; 12/2005

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3 Citations

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Institutions

  • 2005
    • Seoul National University
      • Department of Computer Science and Engineering
      Seoul, Seoul, South Korea