N.A. Fernandez Garcia

Publications (4)0 Total impact

• Conference Proceeding: An efficient FPGA implementation of a DT-CNN for small image gray-scale pre-processing

  J. Albo-Canals, J.A. Villasante-Bembibre, J. Riera-Babures, N.A. Fernandez-Garcia, V.M. Brea
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  ABSTRACT: This paper presents an 8-bit FPGA implementation of a discrete time cellular neural network (DTCNN) suitable for small image gray-scale pre-processing (simple operations with high computational burden). It uses Split&Shift techniques to have a 31 times 31 grid that processes more than 2500 images per second. As this work evolves from a previous binary DTCNN implementation, results are compared in terms of area occupancy, routing complexity and processing time. Several design techniques have been applied to optimize the VHDL implementation on an Altera Stratix II-EP2S60F484C5 FPGA device. Moreover, as technology independent description allows easy migration to other devices or vendors, the benefits of FPGA technology evolution are discussed, focusing on DTCNN implementations.
  Circuit Theory and Design, 2009. ECCTD 2009. European Conference on; 09/2009
• Conference Proceeding: Template-oriented hardware design based on shape analysis of 2D CNN operators in CNN template libraries and applications

  N.A. Fernandez Garcia, M. Suarez, V.M. Brea, D. Cabello
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  ABSTRACT: This work aims at finding efficient configurations of coefficient circuits in a CNN hardware cell implementation based on the shape of the templates listed in the Cellular Wave Computing Library (CSW) and some applications/algorithms addressed in the CNN literature. The paper also touches briefly on possible hardware approaches to take advantage of the shape and symmetries of the templates.
  Cellular Neural Networks and Their Applications, 2008. CNNA 2008. 11th International Workshop on; 08/2008
• Conference Proceeding: Verification of Split&Shift techniques for CNN hardware reduction

  N.A. Fernandez-Garcia, J. Albo-Canals, V.M. Brea, J. Riera-Babures, D. Cabello, X. Vilasis-Cardona
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  ABSTRACT: The so-called split&shift (S&S) methodology has previously been introduced as an effective area saving technique for hardware implementation of cellular non-linear networks. This work provides the first experimental proof of such a methodology through a circuit implementation over an FPGA platform. Results of area, processing time and functionality of different instances of the S&S methodology are given.
  Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on; 09/2007
• Conference Proceeding: Area and Time Efficient Cellular Non-linear Networks

  N.A. Fernandez-Garcia, V.M. Brea, D. Cabello
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  ABSTRACT: The use of a reduced set of multipliers or coefficient circuits on cellular processor arrays leads to time and area efficient solutions. The reduced set of multipliers is achievable with the so-called split&shift (S&S) methodology. Data resultant from applying such a methodology to implementations with cellular non-linear networks (CNN) reported in the literature are presented. Also, pixel-level snakes (PLS) are used as benchmark for a more in-depth analysis of our methodology.
  Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on; 06/2007