M. Gusad

University of the Philippines Diliman, Diliman, Central Luzon, Philippines

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Publications (8)0 Total impact

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    ABSTRACT: Operational amplifiers (op-amps) serve as the basic building blocks in almost every analog and mixed-signal electronic circuit. However, one of the most common problems in op-amp design is the variation in the op-amp's performance caused by process variations during fabrication. As such, it is of utmost importance that provisions be made on the op-amp to compensate for possible deviations in performance after chip fabrication. In this paper, a procedure on integrating programmable bias networks into an operational amplifier is developed. The programmable network driven by digital input words makes the output bias currents and voltages variable, thus making the op-amp tunable for proper operation even after chip fabrication. Furthermore, the programmability of other op-amp parameters such as gain, slew rate, and compensation are explored to increase the capability and flexibility of the op-amp. The programmability schemes are employed on two base op-amp topologies namely, the Two-stage Miller and the Folded Cascode. The project is implemented in a standard 90 nm CMOS process.
    01/2009;
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    ABSTRACT: Analog-to-digital converter designs are considerably becoming critical parts of wireless receiver improvement studies. Delta-sigma ADCs, which offer high-resolution, low cost and low power benefits are tested for aptness for the ZigBee standard - an emerging standard developed to address the needs of wireless sensing and control based on IEEE 802.15.4. Eight fully integrated delta-sigma analog-to-digital converters in 0.25 mum digital CMOS process are presented. The following analog modulator topologies are used: single-ended continuous-time (SECT), single-ended discrete-time (SEDT), fully-differential continuous-time (FDCT), and fully-differential discrete-time (FDDT). For each topology, two digital filters are designed. The converters employ a first-order single-bit delta-sigma conversion. Specifications matched for suitability in ZigBee receivers include data rate, effective number of bits, oversampling ratio, and power consumption.
    Communications and Information Technologies, 2007. ISCIT '07. International Symposium on; 11/2007
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    ABSTRACT: The paper presents the design and implementation of six operational amplifiers with rail-to-rail input and output capability. The study characterizes several rail-to-rail input and output stages and the dependence of the op-amp's operation on different design parameters to formulate a standard design methodology that can serve as a guide for future researches and projects in the area of rail-to-rail amplifiers. The report shows the effects of the rail-to-rail stages on the op-amp's input common-mode range and output voltage swing range. The op-amps are implemented in 0.25 mum CMOS process and the simulation results achieve specifications such as gain, bandwidth, offset voltages and common-mode rejection ratio comparable with commercially available circuits.
    Communications and Information Technologies, 2007. ISCIT '07. International Symposium on; 11/2007
  • Maria Theresa A. Gusad, Louis P. Alarcon
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    ABSTRACT: This paper discusses the effects of the structure of inductors and capacitors on the performance of LNA circuits. Using a 0.25 μm CMOS process, several LNA circuits employing the common-source topology with cascode configuration are designed, implemented, fabricated, and tested. The gain, isolation, and matching characteristics of LNA circuits implemented using different inductor and capacitor structures are characterized. Actual measurement results are compared and analyzed. From data obtained, the use of spiral inductors with patterned ground shield and vertical parallel plate capacitors in implementing LNA circuits are recommended.
    Microwave Conference, 2006. APMC 2006. Asia-Pacific; 01/2007
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    ABSTRACT: Operational amplifiers (op-amps) have proven to be indispensable because of their various applications in the field of electronics. Industrial specifications of op-amps have been continuously improving in almost every metric. This paper discusses the design methodologies developed for standalone, low-power, all-complementary metal-oxide semiconductor (CMOS) op-amps targeting industry-standard specification using two basic op-amp topologies. These design methods were developed from previous theses done at the laboratory and from other universities' publications
    TENCON 2006. 2006 IEEE Region 10 Conference; 01/2006
  • M. Gusad, L.P. Alarcon
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    ABSTRACT: In this paper, the effects of the structure of passive devices on the performance of LNA circuits are investigated. Using a 0.25 mum CMOS process, several LNA circuits employing the common-source topology with cascode configuration are designed, implemented, fabricated, and tested. The gain, isolation, and matching characteristics of LNA circuits implemented using different inductor and capacitor structures are characterized. Actual measurement results are compared and analyzed. From these results, recommendations on the suitable capacitor and inductor structures for LNA circuits are given
    TENCON 2006. 2006 IEEE Region 10 Conference; 01/2006
  • M.T.A. Gusad, L.P. Alarcon
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    ABSTRACT: In this paper, a methodology in designing CMOS low-noise amplifiers (LNAs) is proposed. Three power- matching techniques are considered in the design of the LNA. These are: (1) matching for maximum available gain, (2) matching for a constant gain, and (3) matching for stability. Using a 0.25 mum CMOS process, several LNA circuits employing the common-source topology with cascode configuration are designed, implemented, fabricated, and tested. The performance of LNA circuits designed using the three different techniques are characterized. Simulation and actual measurement results are also compared and analyzed to determine the capability of the simulator to predict the LNA's overall performance at radio frequencies.
    TENCON 2005 2005 IEEE Region 10; 12/2005
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    ABSTRACT: In this paper, four monolithic current-mode instrumentation amplifier (in-amp) topologies are implemented in 0.25um CMOS process, with positive second-generation current conveyors (CCII+) as building blocks. The in-amp topologies are designed to handle biomedical signals, specifically that of the Electrocardiogram (ECG). Four types of CCII+ are characterized and realized using a rail-to-rail op-amp and different types of current mirrors. The Op-Amp with Simple Current Mirror exhibits the highest current swing and the lowest power consumption, and is thus chosen as the optimum CCII+ block to be used in all four in-amps. All current-mode in-amps are implemented using a standard 0.25um CMOS process and yield excellent common-mode rejection ratio (CMRR) greater than 150dB for a differential gain of 100. All four in-amps consumes less than 2.5mW of power for a single voltage supply of 2.5V. However, the 2-Current Conveyor with Op-Amp at the Output (2-CC with Op-Amp) has adjustable output reference voltage and provides the lowest output impedance among the four in-amps.

Publication Stats

14 Citations

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Institutions

  • 2007
    • University of the Philippines Diliman
      • Electrical and Electronics Engineering Institute
      Diliman, Central Luzon, Philippines
    • University of the Philippines – Philippine General Hospital
      Manila, National Capital Region, Philippines
  • 2005
    • Philippine Women's University
      Manila, National Capital Region, Philippines