M.D. Pierson

Publications (2)1.22 Total impact

• Source

  Available from: psu.edu

  Article: Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic

  Tsung-Te Liu, L.P. Alarcon, M.D. Pierson, J.M. Rabaey
  [show abstract] [hide abstract]
  ABSTRACT: This paper presents the design and implementation of a low-energy asynchronous logic topology using sense amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low-leakage pass transistor networks at low supply voltages. The introduction of asynchronous operation in SAPTL further improves energy-delay performance without a significant increase in hardware complexity. We show two different self-timed approaches: 1) the bundled data and 2) the dual-rail handshaking protocol. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation and measurement results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled data self-timed approaches in 90-nm CMOS.
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 08/2009; · 1.22 Impact Factor
• Conference Proceeding: Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic

  Tsung-Te Liu, L.P. Alarcon, M.D. Pierson, J.M. Rabaey
  [show abstract] [hide abstract]
  ABSTRACT: This paper presents the design and implementation of a low energy asynchronous logic architecture using sense amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low leakage pass transistors and low supply voltage. The introduction of asynchronous operation in SAPTL further improves energy-delay performance and reliability without increasing hardware complexity. We show two different self-timed approaches using a bundled-data and a dual-rail handshaking protocol, respectively. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled-data self-timed approaches.
  Asynchronous Circuits and Systems, 2008. ASYNC '08. 14th IEEE International Symposium on; 05/2008