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ABSTRACT: When physically implemented, independent component analysis (ICA) algorithm can achieve a real time blind signal separation (BSS). However, due to the limited size of the hardware device in microelectronics technology, several constraints can be encountered to reach the real time processing since the application of the ICA algorithm requires the consumption of a huge number of input signal samples. Hence, the system performance was degraded since we required the processing of an important number of memory circuits with faster hardware execution time. Therefore, in order to improve the hardware performances of the device, the authors proposed the sequential processing of one neuron hardware model based on field programmable gate array (FPGA) implementation. Such approach overcomes the consumption resources and the interconnections complexities of the FPGA architecture. Thus, an optimal hardware design can be proposed in which a maximum number of samples can be handled while maintaining high speed of hardware processing time. The proposed approach was demonstrated through an experimental study of TIMIT database exhibiting a hardware execution time of 3.3 ¿s to process 10000 samples with 57 kHz of sample rates to separate two output independent signals from two input mixed signals.
Microelectronics, 2008. ICM 2008. International Conference on; 01/2009
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ABSTRACT: The application of independent component analysis (ICA) algorithm can achieve a real time blind signal separation (BSS) if it is physically implemented using hardware devices. However, due principally to both of the limited size and of the microelectronics technology of the used hardware devices, many practical problem can be encountered to reach the real time processing since the application of the ICA algorithm requires the consumption of a huge number of input signal samples. Hence, the system performance was degraded since we required the consumption of an important number of memory circuits with faster hardware execution time. Therefore, in order to improve the hardware performances of the device, in this paper, the authors proposed the sequential processing of one neuron hardware model based on field programmable gate array (FPGA) implementation. Such approach overcomes the interconnections complexities of the FPGA architecture. Thus, an optimal digital circuit design can be proposed to avoid the consumption of much hardware resources in which a maximum number of samples can be handled while maintaining high speed of hardware processing time. The proposed approach was demonstrated through the experimental study of TIMIT data base exhibiting a hardware execution time of 3.3 mus to process 10000 samples with 57 KHz of sample rates to separate two output independent signals from two input mixed signals.
Machine Learning for Signal Processing, 2008. MLSP 2008. IEEE Workshop on; 11/2008
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ABSTRACT: In this paper, we have illustrated the design of the computation of implementation which is principally based on finding correct values of the convergence of the update weights based on Independent Component Analysis (ICA) training algorithm that performs the application of Blind Signal Separation (BSS). We targeted simple computation of implementation, which yields to less complex architecture of the digital of implementation. Over the adjustment of the update weight with the mutual information approach, we reduced the high computation needed for the calculation of ICA training algorithm. The simulation results, obtained from a case study of FPGA implementation, demonstrated the correctness of the adjustment of the update weight with high performance of hardware implementation for BSS algorithm.
Signals, Systems and Electronics, 2007. ISSSE '07. International Symposium on;
