L. Bomholt

ETH Zurich, Zürich, ZH, Switzerland

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Publications (9)2.32 Total impact

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    Victor Moroz · Lars Bomholt
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    ABSTRACT: While current and next generation lithographic techniques mostly focus on increasing resolution, line edge roughness (LER) remains one of the primary problems that limit the progress of scaling. In this paper, we examine the impact of lithographically induced line edge roughness on device performance using 3D TCAD (Technology CAD) simulation. We propose a methodology to reduce line edge roughness and examine the impact using simulation-based atomistic analysis of microscopic surface roughness. We show that several alternative wafer processing options - such as orientation dependent etching, selective epitaxy, and amorphization followed by solid phase epitaxial recrystallization - significantly reduce the lithography-induced line edge roughness. In particular, this is possible for the {111} silicon surfaces, due to their abnormally low etching and epitaxy rates compared to the other crystal orientations. For FinFETs and memory devices, this corresponds to non-standard (110) wafers with structures aligned across the <111> crystal direction. A detailed example is given on how the crystal self-assembly suppresses line edge roughness and cuts the average surface slope by a factor of four during a ten minute selective epitaxy process. The remaining surface roughness is limited to a few atomic steps and enables transistor scaling to the end of the roadmap.
    Proceedings of SPIE - The International Society for Optical Engineering 03/2012; DOI:10.1117/12.916231 · 0.20 Impact Factor
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    L. Sponton · L. Bomholt · W. Fichtner
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    ABSTRACT: In this work we present a study of the combined effects of the variation of process parameters and geometry in a 65 nm technology through consistent three-dimensional TCAD process and device simulations. Channel lengths and widths together with two critical process parameters obtained through a screening experiment are examined in a 3-level full-factorial design of experiments. The results show an increased impact of process variations for short and narrow structures.
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    Yv. Saad · M. Ciappa · P. Pfaffli · L. Bomholt · W. Fichtner
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    ABSTRACT: Technology CAD (TCAD) modeling is used to develop, analyze, and optimize flash memory devices under all operating conditions, taking into account three-dimensional effects such as cross-talk between the cells. A methodology for structure generation, meshing, device simulation, and characterization of flash memory devices is proposed. The results demonstrate the effectiveness of full 3D simulation models for flash memory cells, which capture the geometrical, physical, and electrostatic effects
    Simulation of Semiconductor Processes and Devices, 2006 International Conference on; 10/2006
  • L. Sponton · L. Bomholt · D. Pramanik · W. Fichtner
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    ABSTRACT: For the 65 nm technology node and beyond, new manufacturability problems are arising that strongly impact device and circuit behavior. Among these problems, line-edge and line-width roughness (LER and LWR) are of particular interest as dominant issues affecting parametric yield. In this paper, we investigate LWR effects by applying latest generation, full 3D TCAD technology including lithography simulation. In addition, our results answer open questions concerning the applicability of 2D slicing approximations vis a vis a 3D modeling effort. While LWR has been investigated by TCAD before, our methodology includes a full 3D process simulation (including lithography) without simplifications to generate the final transistor structures
    Simulation of Semiconductor Processes and Devices, 2006 International Conference on; 10/2006
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    ABSTRACT: This paper describes methodology for constructing compact SPICE models as a function of process parameter variations. The methodology involves global extraction of process-dependant SPICE model parameters from silicon calibrated TCAD simulations. The model is validated by comparing device characteristics from the extracted SPICE parameters with those from TCAD simulations. The analysis demonstrates an excellent goodness of fit over the full range of process parameter variations. The process-dependant SPICE models allow direct access to process parameter variations in circuit design. The extracted models are employed in rudimentary digital circuits to investigate the delay variation in response to process deviations. The proposed approach significantly improves design-for-manufacturing (DFM) by allowing for accurate design sensitivity analysis and parametric yield assessment, as a function of statistically independent and measurable process variations.
    Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on; 04/2006
  • R. Borges · T. Ma · Wei-Choon Ng · S. Krishnamurthy · L. Bomholt
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    ABSTRACT: We report a complete TCAD methodology that addresses the considerable manufacturing challenges posed by rising technological complexity, increasing process variability and shrinking time-to-market windows. Using TCAD simulations as input, process compact models are created to enable efficient analysis of complex and multivariate process-device relationships, with applications to enhancing process manufacturability and process control. The methodology is illustrated with two case studies for 90nm CMOS and edge emitting laser technologies
  • Ingo Bork · Victor Moroz · Lars Bomholt · Dipu Pramanik
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    ABSTRACT: Currently, TCAD is most heavily used in the device research and process integration phases of a technology life cycle. However, a major trend visible in the industry is the demand to apply TCAD tools far beyond the integration phase into manufacturing and yield optimization. Short IC product lifetimes make fast yield ramp-up critical for being profitable and TCAD tools build a bridge between IC design and manufacturing. Another major trend is to use TCAD to evaluate layout dependent stress variations and account for these variations in the design flow of standard cells, libraries and custom ICs. This article gives an overview of those trends and addresses resulting challenges for TCAD models and tools.
    Materials Science and Engineering B 12/2005; 124-125:81-85. DOI:10.1016/j.mseb.2005.08.093 · 2.12 Impact Factor
  • Source
    Wolfgang Fichtner · Dipu Pramanik · Lars Bomholt
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    ABSTRACT: Over the past decade, the EDA industry has evolved from offering selections of a few point tools to providing completely integrated software platforms that provide solutions from RTL to silicon. For the 90nm node and beyond, issues with manufacturability and yield force the EDA industry and manufacturing to move closer together. In particular, process and device information that affect functionality and yield need to be incorporated into the design flow, addressing more comprehensively issues of Design for Manufacturability (DFM) and Yield (DFY). At present, DFM focuses mostly on resolution enhancement techniques such as OPC, completely neglecting other factors like process and device variability. In yield terms, this implies that the current focus only covers parts of the parametric yield issues. For true DFM and DFY, it is necessary to look beyond printability issues and include process variability in the design process. Manufacturability issues also require a tighter union of design and manufacturing. The information needed by designers includes layout sensitivities as well as the effect of process variability on the electrical characteristics of devices and interconnects. At the 65nm node the variability will increase significantly as a result of feature scaling and the introduction of new materials and innovative techniques such as strain engineering. TCAD (Technology CAD) addresses these problems as it complements silicon metrology data with accurate calibrated process and device models. In combination with wafer data, the strength of TCAD lies in the accurate prediction of device and interconnect variability due to layout as well as due to random variations in the process. Variability information can then be incorporated into the design tools through appropriate statistical compact models. Ultimately, this leads to an improved design flow that addresses manufacturability issues in a comprehensive way.
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    ABSTRACT: In this paper, the design of a shared technology simulation repository is described. This system allows the download, archival, and simultaneous translation of equipment recipe and run data into a shared, revision controlled repository, as well as the automated generation of Technology Computer Aided Design (TCAD) input. Based on this system Computer Integrated Manufacturing (CIM) data and integrated circuit layout data can be combined to provide rapid technology optimization, enabling new methods of technology development.