Fu-Liang Yang,
Cheng-Chuan Huang,
Chien-Chao Huang,
Tang-Xuan Chung,
Hou-Yu Chen,
Chang-Yun Chang,
Hung-Wei Chen,
Di-Hong Lee,
Sheng-Da Liu,
Kuang-Hsin Chen, [......],
Peng-Fu Hsu, Jyu-Honig Shieh,
S.K.-H. Fung,
C.H. Diaz,
C.-M.M. Wu,
Yee-Chaung See,
B.J. Lin,
M.-S. Liang,
J.Y.-C. Sun,
Chenming Hu
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ABSTRACT: The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 μm<sup>2</sup>. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 μA/μm for N-FET and P-FET, respectively. The P-FET current is the best reported so far.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
