J.H. Tapia

Publications (2)0 Total impact

• Conference Proceeding: Implementation of three SIMD algorithms for graphical user interface processing in mobile devices using the Atsana J2210 media processor

  K.C. Breen, J.H. Tapia, D.G. Elliott
  [show abstract] [hide abstract]
  ABSTRACT: This paper presents the implementation of three single-instruction, multiple-data (SIMD) parallel algorithms for improved graphical user interface processing in mobile devices. These algorithms, which perform alpha blending, window masking and rendering with antialiasing, are adapted for use with Atsana semiconductor's J2210 media processor, a low-power system-on-chip for graphic, image and video processing in wireless applications. All three SIMD algorithms are successfully realized in software for the J2210, without the use of any floating-point math or integer division. The algorithms are evaluated through architecturally-aware simulation of the J2210's SIMD array processor, and their performance is compared to that of equivalent sequential algorithms on a conventional RISC processor. Results show a performance improvement by a factor of 99.6, 39.3 and 2.4 for alpha blending, window masking and rendering with antialiasing, respectively. Power consumption in the array processor is very low for each algorithm, with a maximum of 4.5 mW during active operation. The combination of high performance and low power consumption achieved by these algorithms demonstrates that they are suitable for use in mobile devices equipped with a SIMD-capable media processor such as the J2210
  Electrical and Computer Engineering, 2005. Canadian Conference on; 06/2005
• Conference Proceeding: A multilevel DRAM with hierarchical bitlines and serial sensing

  B.F. Cockburn, J.H. Tapia, D.G. Elliott
  [show abstract] [hide abstract]
  ABSTRACT: We propose a multilevel DRAM (MLDRAM) with serial sensing that has lower area overhead than designs that use single-step, flash conversion sensing. The new design exploits hierarchical, multidivided bitlines to offset the reduction in noise margins caused by multilevel signaling and thereby better preserve the signal-to-noise ratio. The multiple sensing operations required to recover multilevel data are performed serially to re-use sense amplifiers and hence minimize the area overhead of the peripheral circuitry at the cost of increased total read time. In a variation of the proposed design, a subset of the addressed row of cells is read in one sensing step while the remaining cells are recovered later in further sensing steps.
  Memory Technology, Design and Testing, 2003. Records of the 2003 International Workshop on; 08/2003