S. Demuynck,
Z. Tokei,
C Zhao, J. de Marneffe,
H. Struyf,
W. Boullart,
M.O. de Beeck,
L. Carbonell,
N. Heylen,
J. Vaes,
G.P. Beyer,
S. Vanhaelemeersch,
R. Sadjadi,
H Zhu,
P. Cirigliano,
J.S. Kim,
J. Vertommen,
B. Coenegrachts,
E. Pavel,
A. Athayde
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ABSTRACT: In this paper we demonstrate the feasibility of integrating a technique for shrinking the lithography-defined feature size by using a plasma process prior to etch. The technique is based on a sequential deposition and selective removal of a polymer coating formed on the top and sidewalls of the developed resist. This method can be applied to both contacts and trenches and allows tuning of the shrink amount. Yielding damascene trenches down to 45 nm were obtained, shrunk from a 85 nm print, while functional 100 nm contacts were formed starting from a 150 nm print. In both cases excellent within-wafer non-uniformities were achieved.
Semiconductor Manufacturing, 2007. ISSM 2007. International Symposium on; 11/2007
