M. Horiguchi,
T. Sakata,
T. Sekiguchi,
S. Ueda,
H. Tanaka,
E. Yamasaki,
Y. Nakagome,
M. Aoki, I. Kaga,
M. Ohkura, [......],
F. Murai,
T. Tanaka,
S. Iijima,
N. Yokoyama,
Y. Gotoh,
K. Shoji,
T. Kisu,
H. Yamashita,
T. Nishida,
E. Takeda
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ABSTRACT: With the arrival of the multimedia era, high-data-rate memory LSIs
are becoming increasingly important to keep up with high-speed CPUs,
graphics processors, and other consumers of stored data. Video editing
and replaying of high-definition television in particular require a high
bandwidth. This paper presents two circuit technologies for a
synchronously operating high-data-rate 1 Gb DRAM: a
distributed-column-control architecture reducing the burst-mode cycle
time, and a ringing-canceling output buffer ensuring reliable high-speed
data transfer
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 42nd ISSCC, 1995 IEEE International; 03/1995
