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Publications (7)0 Total impact

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    ABSTRACT: Semiconductor device packaging technology is rapidly advancing, in response to the demand for thinner and smaller electronic devices. Three-dimensional chip/wafer stacking that uses through-silicon vias (TSV) is a key technical focus area, and the continuous development of this novel technology has created a need for non-contact characterization. Many of these challenges are novel to the industry due to the relatively large variety of via sizes and density, and new processes such as wafer thinning and stacked wafer bonding. This paper summarizes the developing metrology that has been used during via-middle & via-last TSV process development at EOL/ITRI. While there is a variety of metrology and inspection applications for 3D interconnect processing, the main topics covered here are via CD/depth measurement, thinned wafer inspection and wafer warpage measurement.
    Proc SPIE 05/2011;
  • Y. S. Ku, H. L. Pang, N. P. Smith, L. Binns
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    ABSTRACT: The feasibility of measuring overlay using small (between 1x1μm and 3x3μm total size) targets has been demonstrated4. The symmetry of the image of isolated test features changes with overlay offset. The targets are small enough to be positioned within active areas of the device, and total measurement uncertainty (TMU) is sufficient to allow these targets to be used in characterizing overlay variations in the active device. In this paper we describe further development of this technique and its application to overlay control in 45nm processes. A simple image model has been used to predict how the target images change with overlay error, and to study the unwanted effects of process variation on the measurement. In order to ensure the accuracy of measurements made using the in-chip targets it is necessary to provide for dynamic calibration of the symmetry-to-overlay response. This calibration can be readily achieved by printing multiple targets close together, with each target having a programmed offset that differs by a small amount. In our tests we have used triplets of targets with programmed offsets of 30nm, 50nm and 70nm. Normal targets are printed with a programmed offset of 50nm. A test reticle was designed for double-pass printing of a range of in-chip targets with different sizes and component dimensions, and with designed overlay offsets of 0nm to 100nm in 4nm steps. Standard bar-in-bar targets were printed with every in-chip target to allow the change of symmetry with overlay to be measured directly. Wafers were printed using a 45nm process poly-to-STI stack. Measurements were made in multiple fields and from multiple wafers using an unmodified Nanometrics Caliper élan overlay tool. The test wafers were printed with extremes of process variation. Correlation of the measured image symmetry to the programmed offset under different process conditions shows that the response is sensitive to film changes, as predicted by the image model. Results from production wafers show that the effect of normal process variation is small enough that calibration is not necessary at every location. Placing a few calibration targets in the scribe lines of the device is more than sufficient, allowing the smallest possible space requirement for measurement inside the active area of the device. Detailed study of the change in overlay with programmed offset along a line of test samples with the same design properties shows short-scale variations of order 1-5nm. According to the 2005 ITRS1 these variations account for nearly 50% of the overlay budget for a 45nm process. This effect cannot be described by any model where overlay variations are purely a mathematical function of position, and in process control at this node it will become necessary to use characterization of overlay by measurement instead of models.
    Proc SPIE 06/2007;
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    ABSTRACT: We have demonstrated the feasibility of measuring overlay using small targets with an optical imaging tool has in earlier papers. For 3mum or smaller targets, overlay shifts introduce asymmetry into the target image. The image asymmetry is proportional to the overlay shift and so this effect can be used to measure the overlay. We have used wafers built using production 45nm and 55nm processes to test these targets in production control situations. Targets with different programmed offsets allow the necessary conversion between image asymmetry and overlay shift to be determined empirically on the wafer under test. Measurements made using standard 25mum bar-in-bar targets and 3mum in-chip targets agree to within 10nm (3sigma). By processing results from five or more fields the agreement is improved to 5nm, a level which is limited by a mechanism other than random errors and which is similar to differences between different styles of bar-in-bar targets. Analysis of data from both in-chip and bar-in-bar targets shows similar patterns of overlay variation within the device area. The pattern of overlay variation does not fit mathematical models of overlay as a function of location. The total change of overlay within the field is 10nm, exceeds the overlay budget for critical layers at 45nm design rules. This uncontrolled in-field variation in overlay must be reduced and ideally eliminated if process control is to be achieved. A first step in controlling these errors is having an ability to measure them, and our data shows that this is possible with targets no larger than 3mum in total size.
    Proc SPIE 03/2007;
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    ABSTRACT: The feasibility of measuring overlay using small targets has been demonstrated in an earlier paper1. If the target is small ("smallness" being relative to the resolution of the imaging tool) then only the symmetry of its image changes with overlay offset. For our purposes the targets must be less than 5mum across, but ideally much smaller, so that they can be positioned within the active areas of real devices. These targets allow overlay variation to be tested in ways that are not possible using larger conventional target designs. In this paper we describe continued development of this technology. In our previous experimental work the targets were limited to relatively large sizes (3x3mum) by the available process tools. In this paper we report experimental results from smaller targets (down to 1x1mum) fabricated using an e-beam writer. We compare experimental results for the change of image asymmetry of these targets with overlay offset and with modeled simulations. The image of the targets depends on film properties and their design should be optimized to provide the maximum variation of image symmetry with overlay offset. Implementation of this technology on product wafers will be simplified by using an image model to optimize the target design for specific process layers. Our results show the necessary good agreement between experimental data and the model. The determination of asymmetry from the images of targets as small as 1mum allows the measurement of overlay with total measurement uncertainty as low as 2nm.
    Proc SPIE 04/2006;
  • J.C. Hsu, Y.S. Ku, H.L. Pang
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    ABSTRACT: A measurement system for capacitance traceability based on quantized Hall resistance (QHR) has been established at Center for Measurement Standards (CMS), Taiwan. The system comprises an ac-dc calculable resistor, an ac resistance bridge, a capacitance bridge, and a multi-frequency quadrature bridge. By using the multi-frequency quadrature bridge, the capacitance standards can be precisely determined at frequencies from 500 Hz to 5 kHz
    Precision Electromagnetic Measurements Digest, 2004 Conference on; 01/2004
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    ABSTRACT: We report on precision measurements of the quantum Hall resistance (QHR) in Center for Measurement Standards (CMS) for primary resistance standard establishment. The standard reproduces points of RH(i=2) and RH(i=4) with relative uncertainties, given as one-standard-deviation estimates, of 6×10-9
    01/1998;
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    ABSTRACT: Electrical unit of resistance maintained at the Center for Measurement Standards (CMS, Republic of China) is based on the second plateau of quantized Hall resistance, RH(2). Resistors are directly or indirectly compared with the RH(2). We report the procedure of the dc and ac resistance measurements at the CMS. Uncertainties associated to the measurements are also briefly reported.