G.J.M. Wienk

Universiteit Twente, Enschede, Provincie Overijssel, Netherlands

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Publications (17)9.19 Total impact

  • Wei Cheng, A.J. Annema, G.J.M. Wienk, B. Nauta
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    ABSTRACT: This paper presents an approach to simultaneously cancel flicker noise and IM3 in Gilbert-type mixers, utilizing negative impedances. For proof of concept, two prototype double-balanced mixers in 0.16- μm CMOS are fabricated. The first demonstration mixer chip was optimized for full IM3 cancellation and partial flicker noise cancellation; this chip achieves 9-dB flicker noise suppression, improvements of 10 dB for IIP3, 5 dB for conversion gain, and 1 dB for input P1 dB while the thermal noise increased by 0.1 dB. The negative impedance increases the power consumption for the mixer by 16% and increases the die area by 8% (46 × 28 μm 2). A second demonstration mixer chip aims at full flicker noise cancellation and partial IM3 cancellation, while operating on a low supply voltage (0.67 × VDD); in this chip, the negative impedance increases the power consumption by 7.3% and increases the die area by 7% (50 × 20 μm 2). For one chip sample, measurements show >10-dB flicker noise suppression within ±200% variation of the negative impedance bias current; for ten randomly selected chip samples, >11-dB flicker noise suppression is measured.
    IEEE Journal of Solid-State Circuits 01/2013; 48(10):2390-2402. · 3.06 Impact Factor
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    ABSTRACT: In the receiver path and in spectrum analyzers, typically gain control blocks are used to limit the incident power to the level that the receiver circuitry can handle without degrading the linearity; in the transmitter path stringent power control is also desirable. Although variable-gain amplifiers (VGAs) traditionally implement the gain-control block, attenuators based on FET transistors show superior performances on linearity, power handling capability and power consumption.
    Digest of Technical Papers - IEEE International Solid-State Circuits Conference 01/2012;
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    ABSTRACT: A dual RF-receiver preceded by discrete-step attenuators is implemented in 65nm CMOS and operates from 0.3– 1.0 GHz. The noise of the receivers is reduced by cross-correlating the two receiver outputs in the digital baseband, allowing attenuation of the RF input signal to increase linearity. With this technique a displayed average noise level below -169 dBm/Hz is obtained with +25 dBm IIP3, giving a spurious-free dynamic range of 89 dB in 1 MHz resolution bandwidth.
    International Journal of Production Economics - INT J PROD ECON. 01/2012;
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    Wei Cheng, A.J. Annema, G.J.M. Wienk, B. Nauta
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    ABSTRACT: A negative impedance is used to enable distortion cancellation between the transconductor and the cascode transistor for LNAs with a cascode topology. As a proof of concept, a resistive feedback LNA using this IM3 cancellation technique in a standard 0.16μm CMOS process shows that for 0.1GHz to 1GHz, improvements of 6.3dB to 10dB for IIP3 and 0.2dB to 1dB for gain are achieved without noise degradation. The power consumption for the LNA is increased by 2%, and the die area by about 700μm2.
    Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE; 01/2012
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    ABSTRACT: In a software-defined radio (SDR) receiver it is desirable to minimize RF band-filtering for flexibility, size and cost reasons, but this leads to increased out- of-band interference (OBI). Besides harmonic and intermodulation distortion (HD/IMD), OBI can also lead to blocking and harmonic mixing. A wideband LNA amplifies signal and interference with equal gain. Even a low gain of 6dB can clip OdBm OBI to a 1.2V supply, blocking the receiver. Hard-switching mixers not only translate the wanted signal to baseband but also the interference around LO harmonics. Harmonic rejection (HR) mixers have been used, but are sensitive to phase and gain mismatch. Indeed the HR in shows a large spread, whereas other work only shows results from one chip. This paper describes techniques to relax blocking and HD/IMD, and make HR robust to mismatch.
    Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International; 03/2009
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    ABSTRACT: Both ring oscillators and relaxation oscillators are subsets of RC oscillators featuring large tuning ranges and small areas. Such relaxation oscillators have two advantages with respect to ring oscillators: 1) they have a constant frequency tuning gain; and 2) their phase can be read out continuously due to their triangular (or sawtooth) waveform. A major disadvantage of practical relaxation oscillators is their poor phase-noise compared to ring oscillators.
    Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International; 03/2008
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    ABSTRACT: In this work the phase noise performance of relaxation oscillators has been analyzed resulting in simple though precise phase noise expressions. These expressions have lead to a new relaxation oscillator topology, which exploits a noise filtering technique implemented with a switched-capacitor circuit to minimize phase noise. Measurements on a 65nm CMOS design show a sawtooth waveform, a frequency tuning range between 1 and 12MHz and a rather constant frequency tuning gain. At 12MHz oscillation frequency it consumes 90μW while the phase noise is -109dBc/Hz at 100KHz offset frequency. By minimizing and balancing noise contributions of charge and discharge mechanisms, a nearly minimal FoM of -161dBc/Hz has been achieved, which is a 6dB improvement over state-of-the-art.
    Electronic Notes in Theoretical Computer Science - ENTCS. 01/2008;
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    ABSTRACT: A 0.18 mum CMOS low noise amplifier (LNA) achieves sub-1 dB noise figure over more than an octave of bandwidth without external noise matching components. It is designed for a future radio telescope, requiring millions of cheap LNAs mounted directly on phased array antenna elements. The short distance between antenna and LNA and low frequency below 2 GHz allows for using an LNA with reflective input impedance, increasing the gain with 6 dB. Without any matching network, very low noise figure is achieved over a wide bandwidth. At 90 mW power, sub-1 dB Noise is achieved for 50 Omega source impedance over a 0.8-1.8 GHz band without external coils, and S21>20 dB, OIP2>25 dBm and OIP3>15 dBm. Preliminary results with 150 Omega source impedance show noise temperatures as low as 25 K around 900 MHz.
    Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE; 07/2007
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    ABSTRACT: Nonlinearity and time-variance in radio frequency (RF) circuits leads to unwanted harmonics and intermodulation products, e.g. in power amplifiers and mixers. This paper reviews a recently proposed multipath polyphase circuit technique which can cancel such harmonics and intermodulation products. This will be illustrated using a power upconverter IC as an example. The upconverter works from DC to 2.4 GHz, and the multipath polyphase technique cleans its spectrum up to the 17th harmonic, keeping unwanted spurious responses more than 40dB below the carrier. The technique can also be useful for other applications, and some possible applications will be discussed.
    Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on; 06/2007
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    ABSTRACT: Transmitter circuits using large signal swings and hard-switched mixers are power-efficient, but also produce unwanted harmonics and sidebands, which are commonly removed using dedicated filters. This paper presents a polyphase multipath technique to relax or eliminate filters by canceling a multitude of harmonics and sidebands. Using this technique, a wideband and flexible power upconverter with a clean output spectrum is realized in 0.13-mum CMOS, aiming at a software-defined radio application. Prototype chips operate from DC to 2.4 GHz with spurs smaller than -40 dBc up to the 17th harmonic (18-path mode) or 5th harmonic (6-path mode) of the transmit frequency, without tuning or calibration. The transmitter delivers 8 mW of power to a 100-Omega load (2.54 V<sub>pp-diff</sub> voltage swing) and the complete chip consumes 228 mW from a 1.2-V supply. It uses no filters, but only digital circuits and mixers
    IEEE Journal of Solid-State Circuits 01/2007; · 3.06 Impact Factor
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    ABSTRACT: Switching mixers are power-efficient but produce unwanted harmonics and sidebands. A multipath technique to clean up the spectrum using digital circuits and mixers, but no filters, is applied to a 0.13mum CMOS power upconverter. The circuit delivers 8mW from dc to 2.4GHz with 11% drain efficiency, with spurs <-40dBc over more than 4 octaves in frequency, and consumes 228mW from a 1.2V supply
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International; 03/2006
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    ABSTRACT: In a multi-standard radio transmitter it is common practice to use multiple narrowband PA’s and filters: one for each standard and a switch before them. With the ever increasing number of different standards to be supported, this architecture becomes increasingly unpractical, as support for every new frequency band requires adding a dedicated external filter. Use of these discrete filters reduces the level of integration, thus making it difficult to realize low cost multi-radios on a single RF chip. This paper presents a polyphase multipath technique to relax or eliminate filters by canceling harmonics and sidebands. Using this technique, a wideband and flexible power upconverter with a clean output spectrum is designed in a 0.13μm CMOS for a software defined radio application. Additionally, a 33% duty cycle is used to cancel the problematic 3rd harmonic of the LO. The demonstrator prototype of the proposed power upconverter operates from DC to 2.4GHz with spurs
    Performance Evaluation - PE. 01/2006;
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    ABSTRACT: A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled outputs, which are alternatingly activated by the switches. For ideal switching, the operation is equivalent to a conventional active mixer. This paper analyzes the performance of the switched transconductor mixer, in comparison with the conventional mixer, demonstrating competitive performance at a lower supply voltage. Moreover, the new mixer has a fundamental noise benefit, as noise produced by the switch-transistors and LO-port is common mode noise, which is rejected at the differential output. An experimental prototype with 12-dB conversion gain was designed and realized in standard 0.18-μm CMOS to operate at only a 1-V supply. Experimental results show satisfactory mixer performance up to 4 GHz and confirm the fundamental noise benefit.
    IEEE Journal of Solid-State Circuits 09/2004; · 3.06 Impact Factor
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    ABSTRACT: A new CMOS mixer topology can operate at low supply voltages by using switches connected only to the supplies. Mixing is achieved exploiting two cross-coupled transconductors, which are alternatingly activated by the switches. A down conversion mixer prototype with 12 dB conversion gain was designed and realized in standard 0.18 μm CMOS. It achieves satisfactory mixer performance up to 4 GHz, at a supply voltage of 1 Volt. Moreover, the mixer topology features a fundamental high frequency noise figure benefit.
    VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on; 07/2003
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    ABSTRACT: Mixers are commonly used in communication systems for frequency translation, and usually exploit switching in some form to implement multiplication by a square wave. However, at the low supply voltages required for new CMOS technologies, switches are non- or poorly conducting in the "middle voltage range" between the supply voltages. To solve this problem, gates are often driven outside the supply voltage range, but this results in gate-oxide reliability problems, especially in future technologies with very thin oxides. We propose a new CMOS mixer topology that can operate at low supply voltages, without driving gates outside the supply range. It exploits only switches connected to the supplies, just as in digital CMOS inverters. Mixing is achieved exploiting two cross-coupled transconductors, which are alternatingly activated and de-activated by the switches. A down conversion mixer prototype with 12 dB conversion gain was designed and realized in standard 0.18μm CMOS. It achieves satisfactory mixer performance up to 4GHz, at a supply voltage of 1 Volt. Moreover, the mixer topology features a fundamental high frequency noise figure benefit.
    01/2003;
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    Z. Ru, E.A.M. Klumperink, G.J.M. Wienk, B. Nauta
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    ABSTRACT: Abstract — Two techniques are presented in this paper for a software-defined radio (SDR) receiver robust to out-of-band interference. Voltage gain is realized at IF simultaneously with low-pass filtering to mitigate blockers and out-of-band intermodulation distortion. A 2-stage polyphase harmonic rejection (HR) mixer concept robust to gain error achieves 2nd-6th HR of more than 60dB for 40 samples without trimming or calibration. A prototype 0.4-0.9G zero-IF receiver in 65nm CMOS has 34dB gain, 4dB NF, +3.5dBm IIP3 and +47dBm IIP2 while drawing 50mA from 1.2V.