Publications (3)0 Total impact
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ABSTRACT: Reconfigurable antenna implementation can be separated into three main processes: Antenna design, simulation, and optimization. The objective of this paper is to provide insight into the selections that must be made to implement a reconfigurable antenna, serving as a guideline for future reconfigurable antenna designers as to what needs to be done before a model is constructed, such as choosing a suitable antenna structure and reconfiguration technology, a proper simulation environment, and an adequate optimization algorithm that will allow smooth transitions between reconfigurable states. These selections are directly dependent on the given project requirements. Several options are presented for each case, and particular selections are made based on desired characteristics.
Conference Paper: Power analysis of resonant clocks[Show abstract] [Hide abstract]
ABSTRACT: Resonant clocks are new design techniques for multi-gigahertz clock distributions that are gaining prominence in the design of low power and ultrahigh frequency microprocessors. In the radiofrequency range, new challenges with respect to skews and jitters become greatly pronounced rendering many conventional clocking techniques inadequate. In this work, we present a comparative study of the power dissipation of three resonant clocking techniques: standing wave, rotary wave and dasiaresonant-loadpsila global clock distributions. Specifically, we generated non-overlapping clock signals resonantly to drive transmission gates in the design of our new binary counter. We used a simplified Sunpsilas SwaP Metric to determine the power efficiency of each resonant technique. All of our designs were simulated using Agilent ADS 2006A. Furthermore, our analysis has revealed that the rotary clock design can achieve a power efficiency of a magnitude of two compared to the other resonant clock techniques.Computer and Communication Engineering, 2008. ICCCE 2008. International Conference on; 06/2008
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ABSTRACT: An architecture for a O(1)-loss irreversible n-bit counter is presented in this paper. It is presented as an initial stepping stone application that is suitable for clarifying the potential energy-efficiency advantages of reversible computing. It is based on using fairly standard, irreversible, semi-static CMOS logic. Care is taken to ensure that energy is not dissipated at subsequent counter bits, except those that are actually changing values on a given cycle. The design utilizes two-phase non-overlapping clocks, phi0 and phi1 with fast rise and fall times. For high system level energy-efficiency, the clocks were generated resonantly using the rotary clock scheme. XOR gates serve as phase detectors with AND gates helping to maintain parity checking. Transmission gates ensure a semi-static logic since the logic levels are restored only during the high portion of the clock period. We compared the power dissipation of an 8-bit counter designed using this logic to a standard 8-bit binary counter design using flip-flops in the 50 nm process and recorded a power advantage of about 60%. A prototype will be sent to MOSIS for fabrication to confirm energy advantage of this design after testing.