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Hwa Sung Rhee,
Ho Lee,
Tetsuji Ueno, Dong Suk Shin,
Seung Hwan Lee,
Yihwan Kim,
A. Samoilov,
P.-O. Hansson,
Min Kim,
Hyong Soo Kim,
Nae-In Lee
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ABSTRACT: The effects of mobility boosters such as straining technologies and modified transport direction emerging for 65 nm pFET and beyond on negative bias temperature instability (NBTI) have been investigated. Although compressive silicon nitride film as contact etch stopper layer (CESL) increases the device performance of pFET, NBTI is degraded by excessive hydrogen from CESL depending on gate length and active width. In addition, induced mechanical strain in gate oxide plays an important role in NBTI degradation behavior. From NBTI on <100> p-channel transistor, it is found that NBTI is not influenced by channel direction and mobility change, but degraded by hydrogen incorporated CESL. Recessed SiGe source/drain (S/D) for high-performance pFET gives more resistant nature against NBTI degradation by elevated S/D structure even with compressive CESL containing high amount of hydrogen. The combination among performance booster for targeting device should be carefully balanced by considering performance gain and reliability
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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Sung Dae Suk,
Sung-Young Lee,
Sung-Min Kim,
Eun-Jung Yoon,
Min-Sang Kim,
Ming Li,
Chang Woo Oh,
Kyoung Hwan Yeo,
Sung Hwan Kim, Dong-Suk Shin,
Kwan-Heum Lee,
Heung Sik Park,
Jeorig Nam Han,
C.J. Park,
Jong-Bong Park,
Dong-Won Kim,
Donggun Park,
Byung-Il Ryu
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ABSTRACT: For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process. With 10nm diameter nanowire, saturation currents through twin nanowires of 2.64 mA/mum, 1.11 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. No roll-off of threshold voltages, ~70 mV/dec. of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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ABSTRACT: A novel mass-production-worthy in-situ etch and regrowth technique (InSERT) for recessed SiGe source-drain (SD) PMOS is introduced. The unique source drain extension (SDE) recess results in high drive current (ion) gains of 35 and 38% for shallow recess depths of 30 and 40nm, respectively, while keeping Vth and off leakage equal to those of control Si. InSERT provides three advantages that are higher ion, higher throughput, and no need for implant retuning when compared to the conventional ex-situ dry etch and regrowth technique which exhibits an ion current gain of 23%.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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ABSTRACT: Improving the MBCFET performance further, we have successfully fabricated single-metal-gate high-performance CMOS MBCFET with elevated flat source/drain (EF-S/D) formed by low temperature cyclic selective epitaxial growth (LTC-SEG) of Si. Due to the S/D engineering and LTC-SEG process, we could achieved the symmetric threshold voltage of 0.25V and -0.22V for TiN-gate n-channel MBCFET (nMBCFET) and p-channel MBCFET (pMBCFET), respectively. This single-metal MBCFET simultaneously satisfied the requirements of high-performance (HP) and low operating power (LOP) transistors in ITRS roadmap.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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ABSTRACT: A new novel raised source/drain (RSD) process by using cyclic selective epitaxial growth (CySEG) has been firstly proposed to enhance device performance for 65nm CMOSFETs and beyond. CySEG is effective in reducing the gate poly depletion effect by elevating only the source/drain region without the growth on top of the poly gate. The CySEG process is effectively combined with disposable spacer integration in order to reduce the SEG thermal budget for CMOS scaling. The disposable spacer process with CySEG dramatically enhance the drive current by 23% for pFET and restore the degraded current performance for nFET. The current performance of nFET was further improved by the RSD structure with channel width decrease. The RSD effect on releasing the compressive stress induced by shallow trench isolation (STI) might describe the opposite current performance tendency of scaled nFET.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
