Publications (2)0 Total impact
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Conference Proceeding: A high fidelity decimation filter for sigma-delta converters
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ABSTRACT: This paper reports on results from the algorithmic design and simulation of a two-path poly-phase decimation filter with 24-bit accuracy over the frequency range from dc to approximately 16kHz. The filter is suited for very high precision data conversion applications, and has been designed for use with a fourth-order ΣΔ modulator running at 4096 kHz. This paper also reports on the fixed-point architectural design, comparative bit-level simulations and silicon implementationAdvanced A-D and D-A Conversion Techniques and their Applications, 1994. Second International Conference on; 08/1994 -
Conference Proceeding: Architectural design simulation and silicon implementation of a very high fidelity decimation filter for sigma-delta data converters
[show abstract] [hide abstract]
ABSTRACT: This paper reports on results from the algorithmic design and simulation of a two-path poly-phase decimation filter with 24-bit accuracy over the frequency range from dc to approximately 16 kHz. The filter is suited for very high precision data conversion applications, and has been designed for use with a fourth-order ΣΔ modulator running at 4096 kHz. This paper also reports on the fixed-point architectural design, comparative bit-level simulations and silicon implementationInstrumentation and Measurement Technology Conference, 1994. IMTC/94. Conference Proceedings. 10th Anniversary. Advanced Technologies in I & M., 1994 IEEE; 06/1994
Institutions
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1994
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University of Westminster
London, ENG, United Kingdom
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