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Publications (4)6.19 Total impact

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    ABSTRACT: This paper presents a 700-V high-voltage laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with a p-body_Extension reduce surface field (RESURF) structure. Experimental results demonstrate that the low ON resistance and breakdown voltage (BV)- RON,sp figure of merit approach the ideal Baliga's power law, in addition, breaks the quasi-saturation limitation with enhanced device safe operating area (SOA). The optimal charge balance and geometrical design to achieve the lowest specific ON resistance (RON,sp) with the desired maximum high BV are displayed and discussed by simulations and experimental results. The 2-D simulations confirmed that, compared with conventional triple-RESURF structures, the presented device provides a fourfold reduction in the surface electric field on the source side and a 32% improvement in blocking voltage. The specific ON resistance demonstrates superior 40% lower performance than published Junction Isolation LDMOS device families. In addition, its twofold increase in SOA extension can improve the performance of circuit designs for switching power supply applications.
    IEEE Transactions on Electron Devices 09/2013; 60(9):2847-2853. · 2.06 Impact Factor
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    ABSTRACT: In this paper, important parameters of the p-buried layer of a high-voltage reduced surface field p-n diode are analyzed and discussed in terms of effects on device performance, including breakdown voltage and specific turn-on resistance, Ron,sp. Guidelines for optimizing the vertical position, lateral location, and doping concentration of the p-buried layer are suggested. The experimental results demonstrate that the p-n diode with the proposed p-buried layer optimization design can improve breakdown voltage by 30.7% but only increases 2.7% in specific on-resistance Ron,sp.
    IEEE Transactions on Electron Devices 01/2013; 60(11):3835-3841. · 2.06 Impact Factor
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    ABSTRACT: In this paper, early-stage hot-electron generation is shown to inject electrons into the shallow trench isolation (STI) edge above the drift region that causes the linear-region drain current to increase abruptly in the first moment of the stress for P-LDMOS transistors. After this early-stage carrier trapping, the transistor exhibits normal hot-carrier degradation during the following stress period. To further study this phenomenon, the geometry and the doping profile of the drift region near the STI edge and the polysilicon gate doping area are changed to investigate the initial I<sub>DLIN</sub> increase. Two-dimensional device simulator is used to analyze the experimental results. It is proven that the amount of current increase strongly depends on the distance from the maximum impact ionization generation rate point to the STI.
    IEEE Transactions on Electron Devices 01/2009; · 2.06 Impact Factor
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    ABSTRACT: One chip solution for SMPS (switch mode power supply) has been drawing great attention of the designers with its green mode standby power and high efficiency in the AC-DC adaptor and LED lighting applications. The UHV (ultra-high voltage) foundry process, which enables the integration solution for green compliance SMPS, is proposed in this paper. The technology integrated low voltage CMOS (5 V), medium voltage (40 V) and UHV (700 V) devices in one single process. The UHV technology provides a novel UHV device structure with RESURF (Reduce-SURface-Field) effect to sustain ultra-high breakdown voltage and not to affect the original low/medium voltage devices performance in the same time. Thus, the concept of this novel structure is easily to apply to the other technology nodes and extend its voltage-sustaining range by adjusting the drift length for the RESURF structure. In this research, the 700 V technology has realized the performance that the BVdss (breakdown voltage) is 800 V with Ronsp (on-resistance) of 270 mOhm-cm<sup>2</sup>. In the same time, the process challenge to optimize 700 V device performance against un-balanced mobile charge issue was also discussed.
    VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008