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Publications (3)0 Total impact

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    ABSTRACT: Area-efficient resistor-capacitor DACs (R-C DACs) and low-offset push-pull output buffers for a 10-bit LCD source driver are proposed. Comparing to a 10-bit resistor-string DAC (R-DAC), the 10-bit R-C DAC has a smaller area. A new output buffer with a push-pull function is adopted so that the source driver can drive the pixel with two-dot inversion to save power consumption. To reduce channel to channel deviations, an offset averaging method is adopted in this work. The simulated settling time is under 7 mus so it is suitable for UXGA LCD TV applications. The chip is fabricated using the TSMC 0.35 mum 2P4M CMOS process. The chip area is 1704times262 mum<sup>2</sup>.
    Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on; 06/2009
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    ABSTRACT: A new compact rail-to-rail buffer amplifier for active matrix liquid crystal display source driver applications is proposed. Two complementary buffer amplifiers driving a pair of column lines are used to realize a rail-to-rail driver. The compact buffer amplifier has a large driving capability with the function of charge and discharge provided by the current positive-feedback (CPF). The CPF can increase the charge capability in conventional class-A pMOS input buffer amplifiers and increases the discharge capability in conventional class-A nMOS input buffer amplifiers. The compact rail-to-rail buffer amplifier is implemented using 0.35 mum CMOS 2-poly 4-metal process technology. The quiescent current consumed is 2.8 muA and 3 muA for a pMOS input buffer amplifier and an nMOS input buffer amplifier, respectively.
    VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on; 05/2009
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    ABSTRACT: The design of a compact low-power highspeed class-AB buffer amplifier for driving the large column line loads of large-size TFT-LCD is presented in this paper. The class-AB buffer amplifier can drive large column line loads up to lOOOpF within 1.28 mus. The proposed class-AB buffer amplifier is implemented with a standard 0.35 mum CMOS 2-poly 4-metal process technology and simulated using HSPICE. The measurement results show that the power consumption of 25.67 muW, and exhibits the slew rates of 4.5V/ mus and 5V/ mus for rising and falling edges, respectively, under a lOOOpF load. The active area of this class-AB output buffer amplifier is only 47 x 45 mum<sup>2</sup>.
    Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on; 01/2008