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ABSTRACT: In this paper, we modify a previously proposed decoding algorithm and propose a VLSI architecture to decode the quasi-cyclic low-density parity-check (QC-LDPC) code C used in the IEEE 802.16e standard. The modified decoding algorithm sequentially decodes a plurality of block codes for which its code length is much smaller than that of C. The proposed decoder can achieve a faster speed of convergence, lower decoding latency, higher throughput, and lower number of memory access as compared to the decoders using conventional turbo decoding message passing (TDMP) based on similar hardware complexity.
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on; 06/2008