Chang-Tzu Wang

National Chiao Tung University, Hsin-chu-hsien, Taiwan, Taiwan

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Publications (12)8.7 Total impact

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    ABSTRACT: An N-channel electrostatic discharge (ESD) protection device with DNW sinker has been designed without latch-up risk for 5-V operating condition. With the DNW sinker, the NMOS snapback behavior can be restrained and the holding voltage can be increased. The proposed ESD protection device can sustain 3.6kV human-body-model (HBM) and 325V machine model (MM) ESD tests. With holding voltage of 6.4V, the latch-up test shows the immunity from 7.5V voltage test and 200-mA current test.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: In this work, the MPSCR (modified PMOS with embedded SCR) structure have been verified in a 0.35-um 40-V CDMOS technology. The MPSCR structure with high ESD robustness has been clearly investigated by TLP instrument and TCAD simulator. By the simulation results, the modified P+ electrode layout of cathode side can enhance the turn-on efficiency of embedded SCR path, and avoid the current crowding effect on the surface of device. The proposed device only need to sweep N+ and P+ regions in drain side, and do not need to increase the additional mask layer. For area reduction, the MPSCR device does not need to increase the layout area and it can sustain up to 7.2kV for HBM and 360V for MM under device width of 300μm. Besides, the proposed MPSCR device has a low trigger voltage (Vtl =54-V) and a high second breakdown current (It2=10-A), which can be extensively applied for ESD protection design of PMIC applications.
    01/2011;
  • Chang-Tzu Wang, Tien-Hao Tang, Kuan-Cheng Su
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    ABSTRACT: An electrostatic discharge (ESD) protection circuit with silicon-controlled-rectifier (SCR) device has been designed without latch-up risk. After fabrication in a 0.13-μm CMOS process, the ESD protection circuit with SCR width of 60μm can sustain 6.2kV human-body-model (HBM) and 475V machine model (MM) ESD tests. The latch-up test shows the immunity against 500-mA triggering current under 3.3V supply voltage.
    01/2011;
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    Chang-Tzu Wang, Ming-Dou Ker
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    ABSTRACT: An electrostatic discharge (ESD) protection design for smart power applications with lateral double-diffused MOS (LDMOS) transistors is investigated. With the gate-driven and substrate-triggered circuit techniques, the n-channel LDMOS can be quickly turned on to protect the output drivers during an ESD stress event. The proposed gate-driven and substrate-triggered ESD protection circuits have been successfully verified in a 0.35-μm 5 V/40 V bipolar CMOS DMOS (BCD) process, which can sustain ESD voltages of 4 kV in human-body-model (HBM) and 275 V in machine-model (MM) ESD tests. In addition, the power-rail ESD protection design can also be achieved with a stacked structure to protect 40-V power pins without a latchup issue in the smart power integrated circuits.
    IEEE Transactions on Electron Devices 01/2011; · 2.06 Impact Factor
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    Chang-Tzu Wang, Ming-Dou Ker
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    ABSTRACT: A low-leakage 2× VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit composed of the silicon-controlled rectifier (SCR) device and new ESD detection circuit, realized with only thin-oxide 1× VDD devices, has been proposed with consideration of gate leakage current. By reducing the voltage across the gate oxides of the devices in the ESD detection circuit, the whole power-rail ESD clamp circuit can achieve an ultralow standby leakage current. The new proposed circuit has successfully been verified in a 1-V 65-nm CMOS process, which can achieve 6.5-kV human-body-model and 350-V machine-model ESD levels under ESD stresses, but only consumes a standby leakage current of 0.15 μA at room temperature under normal circuit operating conditions with 1.8-V bias.
    IEEE Transactions on Electron Devices 07/2010; · 2.06 Impact Factor
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    ABSTRACT: A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7 kV human-body-model (HBM) and 325 V machine model (MM) ESD tests which occupying an silicon area of only 49 mum times 21 mum and consuming a very low standby leakage current of 96 nA at room temperature.
    IC Design and Technology, 2009. ICICDT '09. IEEE International Conference on; 06/2009
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    Chang-Tzu Wang, Ming-Dou Ker
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    ABSTRACT: An ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current. By controlling the gate current of the devices in the ESD detection circuit under a specified bias condition, the whole power-rail ESD clamp circuit can achieve an ultra-low standby leakage current. The new proposed circuit has been fabricated in a 1 V 65 nm CMOS process for experimental verification. The new proposed power-rail ESD clamp circuit can achieve 7 kV HBM and 325 V MM ESD levels while consuming only a standby leakage current of 96 nA at 1 V bias in room temperature and occupying an active area of only 49 mum 21 mum.
    IEEE Journal of Solid-State Circuits 04/2009; · 3.06 Impact Factor
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    Ming-Dou Ker, Chang-Tzu Wang
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    ABSTRACT: Two new electrostatic discharge (ESD) protection design by using only 1 times VDD low-voltage devices for mixed-voltage I/O buffer with 3 times VDD input tolerance are proposed. Two different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device. These two ESD detection circuits with different design concepts both have effective driving capability to trigger the ESD clamp device on. These ESD protection designs have been successfully verified in two different 0.13-mum 1.2-V CMOS processes to provide excellent on-chip ESD protection for 1.2-V/3.3-V mixed-voltage I/O buffers.
    IEEE Transactions on Device and Materials Reliability 04/2009; · 1.52 Impact Factor
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    Ming-Dou Ker, Chang-Tzu Wang
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    ABSTRACT: Electrostatic discharge (ESD) protection for mixed-voltage I/O interfaces has been one of the major challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. Moreover, the gate leakage current across thin gate-oxide devices has serious degradation on circuit performance while circuits implementing in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O buffers should meet the gate-oxide reliability constraints and be designed with consideration of gate leakage current. This paper presents the effective ESD protection scheme with circuit solutions to protect the mixed-voltage I/O buffers in nanoscale CMOS processes against ESD stresses. The proposed ESD protection scheme and the specific ESD clamp circuits with low standby leakage current have been successfully verified in nanoscale CMOS processes. Effective on-chip ESD protection scheme should be early planed and started in the beginning phase of chip design in order to achieve good enough ESD robustness for IC products.
    IEEE Custom Integrated Circuits Conference, CICC 2009, San Jose, California, USA, 13-16 September, 2009, Proceedings; 01/2009
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    ABSTRACT: A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1timesVDD devices for 3timesVDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-mum CMOS process with only 1.2-V devices.
    Reliability physics symposium, 2007. proceedings. 45th annual. ieee international; 05/2007
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    Ming-Dou Ker, Chang-Tzu Wang
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    ABSTRACT: A new electrostatic discharge (ESD) protection design by using only 1timesVDD low-voltage devices for mixed-voltage I/O buffer with 3timesVDD input tolerance is proposed. A special ESD detection circuit has been proposed to improve ESD protection efficiency of ESD clamp device by substrate-triggered technique to achieve high ESD level. This design has been successfully verified in a 0.13-mum CMOS process to provide an excellent circuit solution for on-chip ESD protection in the mixed-voltage I/O buffers with 3timesVDD input tolerance.
    Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian; 12/2006
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    ABSTRACT: An ESD protection design for 1.2V/2.5V mixed-voltage I/O interfaces is discussed. A high-voltage-tolerant power-rail ESD clamp circuit is used; it is realized with low-voltage devices in a 0.13mum CMOS process. The four-mode ESD stresses on the mixed-voltage I/O pad and the whole-chip pin-to-pin ESD protection can be discharged by the proposed ESD protection scheme
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International; 03/2006