C.E.S. Felipe

Publications (2)0 Total impact

• Conference Proceeding: Modelling Asynchronous Systems using Probability Distribution Functions

  J.M. Colmenar, C.E.S. Felipe, N. Moron, O. Garnica, J. Lanchares, J.I. Hidalgo
  [show abstract] [hide abstract]
  ABSTRACT: Asynchronous systems are attracting the interest of a growing number of designers. However, the lack of simulation tools devoted to asynchronous microarchitectures is a gap that is not narrowed today. One of the main obstacles on the simulation of asynchronous systems is the variable computation delays of their modules, which compute as fast as possible under the actual conditions of the system because there is no clock signal. In this paper we present a modelling method that describes the variable computation delay of an asynchronous circuit by using probability distribution functions that return the probability of a given delay to be spent on the computation of a data. This method was integrated in an architectural simulator of a 64-bit superscalar asynchronous microarchitecture where the computation delay of each one of the modules of the microarchitecture was characterized through a probability distribution function. The experimental results showed that the asynchronous behavior was successfully modeled, and the architectural simulations of standard benchmarks were affordable in terms of wall-clock simulation time.
  Parallel, Distributed and Network-Based Processing, 2008. PDP 2008. 16th Euromicro Conference on; 03/2008
• Conference Proceeding: Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart

  J.M. Colmenar, C.E.S. Felipe, O. Garnica, J. Lanchares, J.I. Hidalgo, G. Minana, S. Lopez
  [show abstract] [hide abstract]
  ABSTRACT: Nowadays, synchronous processor designers have to deal with severe problems related to the distribution of a complex clock network like skew reduction, high power-consumption, synchronization of clocks, etc. Asynchronous or self-timed architectures are becoming an interesting design alternative because they usually avoid these drawbacks, and they are able to achieve high performance at a low power consumption cost. However, on the first steps of the design process, the evaluation of the performance of such architectures through simulations is much more complicated due to the requirement of modeling the data-dependant timing of each system module. The aim of this paper is to evaluate the performance of a 64-bit fully-asynchronous superscalar processor microarchitecture with dynamically scheduled instruction flow, out-of-order speculative execution of instructions and advanced branch prediction. To tackle this goal we have described the asynchronous microarchitecture solving the synchronization between structures through a four-phase handshake protocol. Then, we have used a modification of the SimpleScalar suite to model the asynchronous microarchitecture in order to run Alpha programs on it. Finally, we have compared the performance of this fully-asynchronous processor with the performance obtained from its synchronous counterpart by running architectural simulations of the SPEC2000 benchmarks on both models
  Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on;