D.J. Schepis,
F. Assaderaghi,
D.S. Yee,
W. Rausch,
R.J. Bolam, A.C. Ajmera,
E. Leobandung,
S.B. Kulkarni,
R. Flaker,
D. Sadana, [......],
J.B. Kuang,
M.C. Hsieh,
K.A. Tallman,
R.M. Martino,
D. Fitzpatrick,
D.A. Badami,
M. Hakey,
S.F. Chu,
B. Davari,
G.G. Shahidi
[show abstract]
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ABSTRACT: In this paper a 0.25 μm SOI CMOS technology is described. It
uses undepleted SOI devices with nominal channel length of 0.15 μm,
minimum channel length in the 0.1 μm range, supply voltage of 1.8 V,
local interconnect, 6 levels of metal, and same ground rules as the
comparable bulk 0.25 μm CMOS. Key technology elements considered
include device, performance, reliability, ESD, and circuit
functionality. Using this SOI CMOS, a 4 Mb SRAM is demonstrated. This is
the highest performance 0.25 μm CMOS technology reported to
date
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International; 01/1998
