Publications (2)0 Total impact
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Conference Proceeding: An FPGA implementation of a soft-in soft-out decoder for block codes
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ABSTRACT: This paper presents an FPGA implementation of the vector SISO algorithm for the (64, 57) extended Hamming code (EH) and (64, 51) extended Bose, Chaudhri, and Hocquenghem code (EBCH). The decoder architecture is defined in VHDL and the circuit is implemented on a Xilinx XC2VP100-1704ff-5 FPGA device. To achieve the required throughput, a pipelined data path architecture operating off a master clock was selected. To reduce gate count, the dynamic range of intermediate results was limited through use of saturation arithmetic. The decoder functionality was verified by means of a test bench that compared the decoded bit stream with error free transmitted signals. SISO decoder design choices that impact the bit error rate (BER) are also presented.Communications, 2008 24th Biennial Symposium on; 07/2008 -
Conference Proceeding: High-speed Viterbi decoder for W-LAN and broadband applications
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ABSTRACT: This paper presents a configurable Viterbi decoder implementation that meets the requirements of the IEEE 802.11b and 802.16a standards. The programmable very high-speed integrated circuit hardware description language (VHDL) design supports a constraint length (K) 7 Viterbi decoder realization with code rates (R) of 1/2 and 1/3, and trace-back lengths (TBL) of 35 and 50 symbols. To assure high throughput, an architecture incorporating 32 add compare select (ACS) units operating in parallel has been selected. Circuit simulation results, based on an Altera FPGA, are presented and confirm a throughput of 160 Mbps.Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on; 07/2004
