[show abstract][hide abstract] ABSTRACT: Input switching activity is one of the deciding factors for power consumption in digital signal processing components. For accurate power estimation, it is essential to have knowledge about the switching activity in the input signal, including how this activity changes in different environments, e.g., in the presence of noise. The dual bit type (DBT) method aims at characterizing the bit-level switching activity in a signal, using signal statistics. However, the DBT method requires that the correlation coefficient and switching activity for the most significant bit of the signal are available. In this paper we give an expression for direct calculation of the correlation coefficient for the most significant bit in a signal, using the word-level correlation coefficient. Using simulation results we examine the accuracy of the given method to calculate the switching activity and correlation coefficient for the most significant bit. Furthermore, we derive expressions for accurately calculating the variance and word-level correlation coefficient for a correlated signal, when an additional noise of a given variance is added to the signal. This can be used to estimate the bit-level switching activity in a signal in the presence of noise. Finally, based on this we study the impact the additional noise has on the switching activity of the resulting signal.
[show abstract][hide abstract] ABSTRACT: Parallel multipliers can be optimized using the intrinsic arith- metic equivalencies in their reduction-tree. In this paper, we propose a method to reduce the dynamic power consumption in parallel multipli- ers, operating within systems with effective word-length variation. Word- length variation induces a certain pattern of spatiotemporal correlations. The proposed method is capable to take such correlations into account resulting better solutions. The experimental results show about 16-21% reduction in the average number of transitions compared to random par- allel multipliers.
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers; 01/2008
[show abstract][hide abstract] ABSTRACT: In this paper we investigate the impact of finite coefficient word length on channel estimator performance. A theoretical analysis of the increase in channel estimation error due to quantization of estimator coefficients is performed, and by using simulation results, the behavior of this error in different fading environments and for different filter orders is studied. Comparing the simulated results with a theoretical model we have shown that there is a relatively good agreement between results based on the theoretical model and the simulated results. We have shown that there is a closer match between theoretical and simulated results when the input signal is less correlated. Our model is restricted to a flat-fading channel with varying Doppler, and linear FIR estimators.
[show abstract][hide abstract] ABSTRACT: In this paper we discuss the impact that fixed point implementation of DSP units in a communication system chain has on the required complexity of channel estimators. We have restricted our model to a flat-fading channel and linear FIR estimators, under the assumption that finite word length effects in the DSP operations in the communication chain can be modeled as additional additive noise. We have shown that a small increase in this noise can lead to a considerable increase in the required estimator complexity if a given NMSE performance for the channel estimation must be upheld, in particular at medium- to-high CSNRs.
Wireless Communication Systems, 2007. ISWCS 2007. 4th International Symposium on; 11/2007