D. Tadesse

Publications (2)0 Total impact

• Conference Proceeding: AutoRex: An automated post-silicon clock tuning tool

  D. Tadesse, J. Grodstein, R.I. Bahar
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  ABSTRACT: Post-silicon clock-tuning is a technique used as part of speed-debug efforts to increase the allowable clock frequency of a chip. These days, it is not uncommon for high-end microprocessors to have cores containing a few thousand clock-tuning elements (i.e., variable-delay buffers). Each such buffer can be assigned to one of several possible discrete delay values, as part of the post-silicon speed debugging process. With the proper mix of assignments, many chips that initially could not meet targeted speed requirements, can now run within specification. With thousands of tunable buffers available on chip, the possible combination of assignments to the delay values is quite large. In addition, process variation causes the same design, once fabricated into silicon, to have different critical paths across different chips. Thus a specific buffer-delay assignment that most improves clock frequency for some chips may not be optimal for all chips. In this paper, we propose a tool we call AutoRex, that produces clock-tuning assignments automatically. AutoRex operates by taking data from a volume experiment across multiple process corners and analyzes this data using satisfiability modulo theory (SMT) solvers to create a single ¿recipe¿ for delay buffer assignments such that the clock frequency of the chip is improved as much as possible over the entire sample of chips. Our results show up to a 9% improvement in frequency using AutoRex.
  Test Conference, 2009. ITC 2009. International; 12/2009
• Source

  Available from: R.Iris Bahar

  Conference Proceeding: Fast Measurement of the Non-Deterministic Zone in Microprocessor Debug Using Maximum Likelihood Estimation

  D. Tadesse, R.I. Bahar, J. Grodstein
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  ABSTRACT: Speed debug is a critical part of microprocessor diagnosis and debug. During this stage, the test engineer must determine and increase the maximum speed at which the processor can run reliably. One of the difficulties of this stage is that the pass-fail boundary, in practice, is not abrupt, but rather encompasses a non-deterministic region of behavior. Accurately modeling this non-deterministic region is particularly important since it directly influences the amount of time needed for speed debug. Current chip debug efforts often rely on the use of brute force techniques to deduce the shape of the pass-fail boundary region. More specifically, speed debug (i.e., the process of finding and fixing critical paths that prevent a chip from running at a higher frequency) requires a thorough understanding of the width and shape of the pass-fail boundary region where the chip's behavior is non- deterministic. In this paper, we propose a statistical method based on maximum likelihood estimation (MLE) techniques to infer the underlying shape of the non-deterministic region. Our method was tested on pre-production Intel microprocessors and was successful in modeling the shape of the fuzz-region in substantially fewer iterations compared to a brute force approach.
  VLSI Test Symposium, 2008. VTS 2008. 26th IEEE;