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ABSTRACT: A multiband flexible RF-sampling receiver aimed at software-defined radio is presented. The wideband RF sampling function is enabled by a recently proposed discrete-time mixing downconverter. This work exploits a voltage-sensing LNA preceded by a tunable LC pre-filter with one external coil to demonstrate an RF-sampling receiver with low noise figure (NF) and high harmonic rejection (HR). The second-order LC filter provides voltage pre-gain and attenuates the source noise aliasing, and it also improves the HR ratio of the sampling downconverter. The LNA consists of a simple amplifier topology built from inverters and resistors to improve the third-order nonlinearity via an enhanced voltage mirror technique. The RF-sampling receiver employs 8 times oversampling covering 300 to 800 MHz in two RF sub-bands. The chip is realized in 65 nm CMOS and the measured gain across the band is between 22 and 28 dB, while achieving a NF between 0.8 to 4.3 dB. The IIP2 varies between +38 and +49 dBm and the IIP3 between -14 dBm and -9 dBm, and the third and fifth order HR ratios are more than 60 dB. The LNA and downconverter consumes 6 mW, and the clock generator takes 12 mW at 800 MHz RF.
IEEE Journal of Solid-State Circuits 06/2010; · 3.23 Impact Factor
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ABSTRACT: A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative ¿iterative¿ harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and + 3.5 dBm in-band IIP3 while the out-of-band IIP3 is +16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > 60 dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply.
IEEE Journal of Solid-State Circuits 01/2010; · 3.23 Impact Factor
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ABSTRACT: A 300-800 MHz CMOS radio receiver aiming at software-defined radio is proposed. It exploits an LNA preceded by a tunable LC filter with one external coil to achieve voltage amplification for low NF and low-pass filtering to improve the 3<sup>rd</sup> and 5<sup>th</sup> harmonic rejection of an RF-sampling receiver to > 60dB. The balun-LNA provides partial IM3 compensation, to drive a wideband sampling downconverter. The measured gain is 22-28dB while NF ranges from 0.8-4.3dB. The core consumes 6mW and clock takes 12mW.
Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE; 07/2009
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ABSTRACT: Spurious-free dynamic range (SFDR) is a key specification of radio receivers and spectrum analyzers, characterizing the maximum distance between signal and noise+distortion. SFDR is limited by the linearity (intercept point IIP3 mostly, sometimes IIP2) and the noise floor. As receivers already have low noise figure (NF) there is more room for improving the SFDR by increasing the linearity. As there is a strong relation between distortion and voltage swing, it is challenging to maintain or even improve linearity intercept points in future CMOS processes with lower supply voltages. Circuits can be linearized with feedback but loop gain at RF is limited. Moreover, after LNA gain, mixer linearity becomes even tougher. If the amplification is postponed to IF, much more loop gain is available to linearize the amplifier. This paper proposes such an LNA-less mixer-first receiver. By careful analysis and optimization of a passive mixer core for low conversion loss and low noise folding it is shown that it is possible to realize IIP3>11 dBm and NF<6.5dB, i.e. a remarkably high SFDR>79dB in 1MHz bandwidth over a decade of RF frequencies.
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International; 03/2009
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ABSTRACT: In a software-defined radio (SDR) receiver it is desirable to minimize RF band-filtering for flexibility, size and cost reasons, but this leads to increased out- of-band interference (OBI). Besides harmonic and intermodulation distortion (HD/IMD), OBI can also lead to blocking and harmonic mixing. A wideband LNA amplifies signal and interference with equal gain. Even a low gain of 6dB can clip OdBm OBI to a 1.2V supply, blocking the receiver. Hard-switching mixers not only translate the wanted signal to baseband but also the interference around LO harmonics. Harmonic rejection (HR) mixers have been used, but are sensitive to phase and gain mismatch. Indeed the HR in shows a large spread, whereas other work only shows results from one chip. This paper describes techniques to relax blocking and HD/IMD, and make HR robust to mismatch.
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International; 03/2009
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ABSTRACT: Wideband direct-conversion harmonic-rejection (HR) receivers for software- defined radio aim to remove or relax the pre-mixer RF filters, which are inflexible, bulky and costly. HR schemes are often used, but amplitude and phase mismatches limit HR to between 30 and 40 dB. A quick calculation shows that much more rejection is wanted: in order to bring harmonic responses down to the noise floor (e.g. -100 dBm in 10 MHz for 4 dB NF), and cope with interferers between -40 and 0 dBm, an HR of 60 to 100 dB is needed. Also in terrestrial TV receivers and in applications like DVB-H with co-existence requirements with GSM/WLAN transmitters in a small telephone, high HR is needed. In this work, an architecture aiming for >80 dB HR is shown. It consists of an analog front-end followed by adaptive interference cancellation (AIC) in the digital domain. AIC is known for its ability to adapt to and mitigate unknown system non-idealities, e.g. gain and phase imbalances. Due to its adaptivity it can achieve large improvements, provided the interference estimate is accurate. To the authors' knowledge, they are the first to explore AIC for HR and previously presented simulation results. Here a new and different architecture and measured results with the RF part implemented in 65 nm CMOS and the AIC in software are presented.
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International; 03/2009
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ABSTRACT: The proposed SDR downconverter is aimed for the DVB-H standard (470 to 862MHz) and for emerging cognitive radio applications in the 200-to-900MHz band, which suffer from 3rd and 5th harmonic mixing. An inverter-based RF-amplifier (RFA) drives a passive switched-capacitor (SC) core consisting of three stages. The first stage is effectively an oversampler, second stage consists of I/Q DT mixers for downconversion and the third stage is a low-pass IIR filter. The chip fabricated in a 65nm CMOS process occupies an active area of 0.36mm<sup>2</sup>. The noise and linearity performances are competitive with those of continuous-time mixers at reasonable power consumption, which shows the feasibility of the proposed architecture for a practical receiver front-end.
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International; 03/2008
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ABSTRACT: CMOS radio receiver architectures, based on radio frequency (RF) sampling followed by discrete-time (D-T) signal processing via switched-capacitor circuits, have recently been proposed for dedicated radio standards. This paper explores the suitability of such D-T receivers for highly flexible software-defined radio (SDR) receivers. Via symbolic analysis and simulations the authors analyze the properties of D-T receivers, and show that at least three challenges exist to make a D-T receiver work for SDR: 1) the sampling clock frequency is related to the radio frequency, complicating baseband filter design; 2) a frequency-dependent phase shift is introduced by pseudo-quadrature and pseudo-differential sampling; 3) the conversion gain of a charge sampling front-end is strongly frequency-dependent. Compared to a mixer based radio receiver, extra costs are needed to solve these problems.
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on; 06/2007
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Z. Ru
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ABSTRACT: There has been a growing demand for wireless communications and diverse communication standards have been developed over time, e.g. GSM, Bluetooth, Wi-Fi, etc. For convenience of use, people desire a universal radio to be able to communicate anywhere using any standard. A software-defined radio (SDR) which aims at greater programmability can meet such a demand. However, there are a number of technical challenges to make a SDR receiver practical. This thesis focuses on frequency translation (FT) techniques and addresses two key SDR challenges: the robustness to out-of-band interference (OBI) and the compatibility with CMOS scaling and system-on-chip (SoC) integration. The thesis studies the principles and the performance limitations of existing FT techniques and proposes new circuit-and-system techniques to improve SDR receivers. Fundamental differences between various FT techniques are highlighted by means of a classification and comparison of mixing and sampling. This leads to the definition of a new discrete-time (DT) mixing technique. The suitability of RFmixing and RF-sampling receivers to SDR is evaluated. RF sampling seems to be more compatible with CMOS scaling and SoC integration. However, existing RFsampling techniques are narrowband and are not directly suitable for a wideband SDR receiver. To address this issue, a DT-mixing technique is proposed which performs a mixing operation in the DT domain after RF sampling. It can make RF sampling more suitable to wideband SDR receivers because it has two properties: wideband phase shifting and wideband harmonic rejection (HR). DT mixing can be realized using de-multiplexing of samples. To verify the concept, a 200-to-900MHz DT-mixing downconverter with 8-times oversampling and 2nd-to-6th HR is implemented in 65nm CMOS. To construct a complete RF-sampling receiver, a tunable LC filter and a linearized low-noise amplifier (LNA) are applied as pre-stages of the DTVIII mixing downconverter. The LC filter employs an external coil and on-chip switchable capacitors. The LNA employs cascaded inverter stages linearized via an enhanced voltage mirror. The RF-sampling receiver achieves a minimum NF as low as 0.8dB and improves HR by 30dB compared to the downconverter alone. To be more robust to OBI, two FT techniques are proposed: one to improve the out-of-band linearity and the other to make the HR robust to mismatch. A low-pass blocker filtering technique is proposed to avoid voltage gain at radio frequencies (RF) but make voltage gain only at baseband simultaneously with low-pass filtering to attenuate OBI. The low voltage gain at RF is realized by means of a low “mix-impedance”, which is analyzed quantitatively. A 2-stage polyphase HR technique is proposed to perform HR in cascaded stages to dramatically improve the amplitude accuracy. To also achieve the high phase accuracy, a simple and accurate frequency divider is presented. The effects of random amplitude and phase errors to HR are analyzed. To demonstrate these concepts, a 65nm CMOS receiver based on RF mixing shows +3.5dBm in-band IIP3 and +16dBm out-of-band IIP3. More than 60dB HR ratio is measured over 40 randomly-selected chips. The multiphase clock generator works up to 0.9GHz while the -3dB RF bandwidth is measured up to 6GHz.
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ABSTRACT: Abstract — Two techniques are presented in this paper for a software-defined radio (SDR) receiver robust to out-of-band interference. Voltage gain is realized at IF simultaneously with low-pass filtering to mitigate blockers and out-of-band intermodulation distortion. A 2-stage polyphase harmonic rejection (HR) mixer concept robust to gain error achieves 2nd-6th HR of more than 60dB for 40 samples without trimming or calibration. A prototype 0.4-0.9G zero-IF receiver in 65nm CMOS has 34dB gain, 4dB NF, +3.5dBm IIP3 and +47dBm IIP2 while drawing 50mA from 1.2V.
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ABSTRACT: Abstract of WO 2010089700 (A1) A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.
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ABSTRACT: Abstract. A multiband flexible RF-sampling receiver aimed at software-defined radio is presented. The wideband RF sampling function is enabled by a recently proposed discrete-time mixing downconverter. This work exploits a voltage-sensing LNA preceded by a tunable LC pre-filter with one external coil to demonstrate an RF-sampling receiver with low noise figure (NF) and high harmonic rejection (HR). The second-order LC filter provides voltage pre-gain and attenuates the source noise aliasing, and it also improves the HR ratio of the sampling downconverter. The LNA consists of a simple amplifier topology built from inverters and resistors to improve the third-order nonlinearity via an enhanced voltage mirror technique. The RF-sampling receiver employs 8 times oversampling covering 300 to 800 MHz in two RF sub-bands. The chip is realized in 65 nm CMOS and the measured gain across the band is between 22 and 28 dB, while achieving a NF between 0.8 to 4.3 dB. The IIP2 varies between +38 and +49 dBm and the IIP3 between -14 dBm and -9 dBm, and the third and fifth order HR ratios are more than 60 dB. The LNA and downconverter consumes 6 mW, and the clock generator takes 12 mW at 800 MHz RF.
