J. J. Wortman

North Carolina State University, Raleigh, North Carolina, United States

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Publications (132)195.41 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: The application of low-frequency charge pumping to obtain near-interface, or bulk trap densities, on thin stacked gate dielectrics is studied. A review of the theory governing the low-frequency charge pumping technique, developed to extract bulk trap densities from metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated with thick SiO<sub>2</sub> dielectrics, is given. In this study, the technique is applied to a series of n-channel MOSFETs fabricated with stacked gate dielectrics. The dielectric stacks were comprised of rapid thermal oxide (RTO) interface layers and rapid thermal chemical vapor deposited (RTCVD) oxynitride layers, which incorporated varying concentrations of nitrogen. The effect of DC tunneling currents on the technique is studied, and a procedure to remove these components from the measured substrate current is outlined. Distortions in the experimentally measured charge pumping current plotted as a function of gate bias is modeled and found to be due to the contribution of bulk traps. Finally, the limitations of applying a model that was originally developed for thick SiO<sub>2</sub> dielectrics to thin stacked gate dielectrics are discussed
    IEEE Transactions on Electron Devices 01/2002; · 2.06 Impact Factor
  • Nian Yang, Jimmie J Wortman
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    ABSTRACT: This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.
    Microelectronics Reliability 01/2001; · 1.14 Impact Factor
  • K. Ahmed, J.J. Wortman, J.R. Hauser
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    ABSTRACT: Based on two-dimensional (2-D) numerical simulation, a pulsed-drain current (PDC) measurement technique in weak inversion is investigated as an alternative to the standard charge-pumping technique for the extraction of interface trap density using small geometry MOSFETs. The PDC technique was found particularly useful for small MOSFETs with sub-20 Å oxides to avoid high gate tunneling current effects. The numerical simulation results are in excellent agreement with the simple analytical expressions used in the PDC technique
    IEEE Transactions on Electron Devices 12/2000; · 2.06 Impact Factor
  • N. Yang, W.K. Henson, J.J. Wortman
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    ABSTRACT: This work examines different components of leakage current in scaled n-MOSFET's with ultrathin gate oxides (1.4-2.0 nm). Both gate direct tunneling and drain leakage currents are studied by theoretical modeling and experiments, and their effects on the drain current are investigated and compared. It concludes that the source and drain extension to the gate overlap regions have strong effects on device performance in terms of gate tunneling and off-state drain currents
    IEEE Transactions on Electron Devices 09/2000; · 2.06 Impact Factor
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    ABSTRACT: Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications
    IEEE Transactions on Electron Devices 08/2000; · 2.06 Impact Factor
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    ABSTRACT: In this work, five methods for measuring the thickness of ultra-thin gate oxide layers in MOS structures were compared experimentally on n<sup>+</sup> poly-SiO<sub>2</sub>-p-Si structures. Three methods are based on electrical capacitance-voltage (C-V) and current-voltage (I-V) data and the other two methods are HRTEM and optical measurement. MOS capacitors with oxide thickness in the range 17-55 Å have been used in this study. We found that thickness extracted using QM C-V and HRTEM agree within 1.0 Å over the whole thickness range when a dielectric constant of 3.9 was used. Comparison between thickness extracted using quantum interference (QI) I-V technique and optical measurement were also within 1.0 Å for thickness 31-47 Å. However, optical oxide thickness was consistently lower than the TEM thickness by about 2 Å over the thickness range under consideration. Both optical measurement and QM C-V modeling yield the same thickness as the nominal oxide thickness increases (>50 Å)
    IEEE Transactions on Electron Devices 08/2000; · 2.06 Impact Factor
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    ABSTRACT: The purpose of this study, based on two-dimensional (2-D) simulation, was to scale effective channel length and series resistance extraction routines for sub-100 nm CMOS devices. We demonstrate that L <sub>eff</sub>- and R<sub>sd</sub>-gate-bias dependence extracted using a modified shift-and-ratio (M-S&R) method may not give accurate results because of a nonnegligible effective mobility dependence on gate bias. Using a reasonable gate bias-dependent mobility model, one observes a finite V<sub>g</sub> dependence of L<sub>eff</sub> and R<sub>sd</sub> even for devices with degenerately doped drain junction
    IEEE Transactions on Electron Devices 05/2000; · 2.06 Impact Factor
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    ABSTRACT: The effects of remote charge scattering on the electron mobility of n-MOSFETs with ultrathin gate oxides from 1.5 nm to 3.2 nm have been estimated. By calculating the scattering rate of the two-dimensional (2-D) electron gas at the Si/silicon dioxide interface due to the ionized doping impurities at the poly-Si/silicon dioxide interface, the remote charge scattering mobility has been calculated. Electron mobility measured from the n-MOSFETs with ultrathin gate oxides has been used to extract several known mobility components. These mobility components have been compared to the calculated remote charge scattering mobility. From these comparisons, it is clear that the overall electron mobility is not severely degraded by remote charge scattering for the oxide thickness studied
    IEEE Transactions on Electron Devices 03/2000; · 2.06 Impact Factor
  • W.K. Henson, N. Yang, J.J. Wortman
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    ABSTRACT: Ultra-thin gate oxide breakdown in nMOSFET's has been studied for an oxide thickness of 1.5 nm using constant voltage stressing. The pre- and post-oxide breakdown characteristics of the device have been compared, and the results have shown a strong dependence on the breakdown locations. The oxide breakdown near the source/drain-to-gate overlap regions was found to be more severe on the post-breakdown characteristics of the device than breakdown in the channel. This observation may be related to the dependence of breakdown on the distribution of electric field and areas of different regions within the nMOSFET under stress.
    IEEE Electron Device Letters 01/2000; · 2.79 Impact Factor
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    ABSTRACT: Ultrathin oxynitride using plasma assisted deposition was evaluated against thermal oxide and nitrided thermal oxide as an alternative direct tunneling gate dielectric to thermal oxide in the 2.5-nm regime. The oxynitride showed an enhanced high field effective mobility relative to the thermal oxide although the low field mobility was slightly depressed. The N/sub 2/O nitrided oxide showed an enhanced high field effective mobility with no degradation in low field mobility. The interface state density of the oxynitride was equivalent to that of the thermal and nitrided thermal oxides; a very welcome observation for this deposition chemistry and anneal conditions.
    IEEE Electron Device Letters 10/1999; · 2.79 Impact Factor
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    ABSTRACT: Gate oxide scaling in NMOSFETs causes electrons to tunnel from the conduction and valence bands of the silicon substrate in the direct-tunneling regime. In NMOSFETs, the tunneling of electrons from the substrate's valence band is a source of the substrate current IB and contributes to the gate current IG. Oxide thickness scaling leads to an increase in the substrate current IB and in the ratio of substrate to gate current. In this paper, we report the trends in the ratio due to oxide thickness scaling in ultrathin SiO2 and composite gate dielectrics.
    Microelectronic Engineering 09/1999; 48:295-298. · 1.22 Impact Factor
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    ABSTRACT: The use of SiGe gates in MOSFET technology has promise as a single-gate material for both n- and p-channel MOSFETs. The Ge content in the gate, however, affects the gate energy band diagram. While Ge in the SiGe gate does not affect the conduction-band energy level, it is found to raise the valence-band energy level and reduce the gate bandgap. This change results in an increase in the gate current resulting mainly from the tunneling of electrons from the valence band of the gate in PMOSFETs. This paper reports on the effects of Ge content in SiGe gates on the tunneling characteristics of PMOSFETs.
    Microelectronic Engineering 09/1999; 48(s 1–4):39–42. · 1.22 Impact Factor
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    ABSTRACT: This paper discusses the limitations on MOSFET test structures used in extracting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion, especially for ultrathin gate oxides. It is shown that for sub-20-Å oxide MOS devices, transistors with channel lengths less than about 10 μm will be needed to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length has been estimated using a new simple transmission-line-model of the terminal capacitance, which accounts for the nonnegligible gate tunneling current and finite channel resistance
    IEEE Transactions on Electron Devices 09/1999; · 2.06 Impact Factor
  • N. Yang, W.K. Henson, J.R. Hauser, J.J. Wortman
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    ABSTRACT: Using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates. The modeled direct tunneling currents have been compared to experimental data obtained from nMOSFET's with direct tunnel gate oxides. Excellent agreement between the model and experimental data for gate oxides as thin as 1.5 nm has been achieved. Advanced capacitance-voltage techniques have been employed to complement direct tunneling current modeling and measurements. With capacitance-voltage (C-V) techniques, direct tunneling currents can be used as a sensitive characterization technique for direct tunnel gate oxides. The effects of both silicon substrate doping concentration and polysilicon doping concentration on the direct tunneling current have also been studied as a function of applied gate voltage
    IEEE Transactions on Electron Devices 08/1999; · 2.06 Impact Factor
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    ABSTRACT: High-frequency capacitance-voltage (C-V) measurements have been made on ultrathin oxide metal-oxide-semiconductor (MOS) capacitors. The sensitivity of extracted oxide thickness to series resistance and gate leakage is demonstrated. Guidelines are outlined for reliable and accurate estimation of oxide thickness from C-V measurements for oxides down to 1.4 nm.
    IEEE Electron Device Letters 05/1999; · 2.79 Impact Factor
  • N. Yang, W.K. Henson, J.J. Wortman
    [Show abstract] [Hide abstract]
    ABSTRACT: This work examines different components of direct tunneling currents and analyzes the oxide reliability in scaled NMOSFETs with ultrathin gate oxides (1.4-2 nm). It concludes that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability
    Electron Devices Meeting, 1999. IEDM Technical Digest. International; 02/1999
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    ABSTRACT: This paper introduces a method for the determination of the gate oxide thickness, X<sub>ox</sub>, of N- and P-Channel MOSFETs with ultrathin oxides based on the characterization and modeling of the substrate current resulting from valence-band electron tunneling (VBET) in the direct-tunneling (DT) regime. Under certain bias conditions, valence-band electron tunneling becomes the main constituent of the substrate currents in N- and P-MOSFETs. This method has several advantages over other methods for the determination of X<sub>ox</sub>, and yields values of X<sub>ox</sub> that agree well with those obtained from modeling capacitance-voltage characteristics, C(V), while taking quantum-mechanical effects into account. Its main advantage is that it is not limited by the oxide thickness
    Electron Devices Meeting, 1999. IEDM Technical Digest. International; 02/1999
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    ABSTRACT: Slow traps and interface traps density has been measured using low frequency (10 Hz) noise and charge pumping measurements. The study has been carried out on n-channel metal-oxide-semiconductor transistors with ultra thin gate dielectrics prepared by rapid thermal oxidation (RTO) and low pressure rapid thermal chemical vapor deposition. For both deposition methods, the interface trap characteristics have been studied as a function of nitrogen concentration as well as thermal annealing parameters (ambient and temperature). Experimental results have shown that a stacked dielectric combined RTO gate oxide (grown under N2O) and chemical vapor deposition oxynitride (capping layer with 8% atomic nitrogen concentration), offers a solution for gate dielectrics with thickness ⩾2 nm.
    Journal of Non-Crystalline Solids 01/1999; 245:54-58. · 1.72 Impact Factor
  • Source
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    ABSTRACT: This study reports on n-channel MOS transistors using very thin oxynitride gate dielectrics deposited by Low-Pressure Rapid Thermal Chemiical Vapor Deposition (LPRTCVD). The threshold voltage, the transconductance, the fast and slow trap densities, the low field mobility and its reduction factors have been investigated as a function of the nitrogen concentration in the film. The threshold voltage was found to decrease linearly with the nitrogen concentration, primarily because of the increase of the positive insulator charge density. At the same time, it has been shown that the quadratic mobility reduction factor is lower for a LPRTCVD oxynitride (and nearly constant with the nitrogen concentration) in comparison to a thermal oxide. From this high field mobility attenuation, a lower transconductance is then expected for oxynitride-based transistors. Finally, we have shown that the presence of nitrogen in the oxide seems to induce more donor than acceptor traps at the oxynitride-silicon interface.
    Microelectronic Engineering 01/1999; 48:211-214. · 1.22 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Gate oxide scaling in NMOSFETs causes electrons to tunnel from the conduction and valence bands of the silicon substrate in the direct-tunneling regime. In NMOSFETs, the tunneling of electrons from the substrate's valence band is a source of the substrate current IB and contributes to the gate current IG. Oxide thickness scaling leads to an increase in the substrate current IB and in the ratio IBIG of substrate to gate current. In this paper, we report the trends in the IBIG ratio due to oxide thickness scaling in ultrathin SiO2 and SiO2Ta2O5 composite gate dielectrics.
    Microelectronic Engineering - MICROELECTRON ENG. 01/1999; 48(1):295-298.

Publication Stats

1k Citations
195.41 Total Impact Points

Institutions

  • 1983–2001
    • North Carolina State University
      • • Department of Electrical and Computer Engineering
      • • Department of Physics
      • • Department of Materials Science and Engineering
      Raleigh, North Carolina, United States
  • 1999–2000
    • Advanced Micro Devices
      Sunnyvale, California, United States
    • Duke University
      • Department of Electrical and Computer Engineering (ECE)
      Durham, NC, United States
  • 1995
    • Johns Hopkins University
      Baltimore, Maryland, United States
    • Cea Leti
      Grenoble, Rhône-Alpes, France
  • 1986–1994
    • University of North Carolina at Chapel Hill
      • • Department of Chemistry
      • • Department of Physics and Astronomy
      Chapel Hill, NC, United States
  • 1983–1985
    • Oak Ridge National Laboratory
      • Solid State Division
      Oak Ridge, Florida, United States