[Show abstract][Hide abstract] ABSTRACT: This letter reports a study on the effect of a hydrogen anneal after silicon pillar etch of surround-gate vertical MOSFETs intended for RF applications. A hydrogen anneal at 800°C is shown to give a 30% improvement in the drive current of 120-nm n-channel transistors compared with transistors with out the hydrogen anneal. The value of drive current achieved is 250 μA/μm, which is a record for thick pillar vertical MOSFETs. This improved performance is obtained even though a sacrificial oxidation was performed prior to the hydrogen anneal to smooth the pillar sidewall. The values of subthreshold slope and DIBL are 79 mV/decade and 45 mV/V, respectively, which are significantly better than most values reported in the literature for comparable devices. The H<sub>2</sub> anneal is also shown to decrease the OFF-state leakage current by a factor of three.
IEEE Electron Device Letters 04/2011; · 2.79 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This paper presents a fast and compact charger architecture for ultracapacitors with direct connection to 230V AC mains supply. The charger delivers a DC output current which allows compensation for inductive and other non-ideal behaviour in the EDLC at medium and high frequencies. The internal converter uses self oscillating control circuits which provide a variable switching frequency over a broad range. This allows the circuit to adapt to the variation of the output voltage (0-16.2V) and fluctuations of the mains network, thereby minimizing losses over the whole operating envelope.
20th European Conference on Circuit Theory and Design, ECCTD 2011, Linkoping, Sweden, Aug. 29-31, 2011; 01/2011
[Show abstract][Hide abstract] ABSTRACT: A ring oscillator is designed and implemented on standard 130nm CMOS technology for wide range frequency tuning purpose in a spectrum monitor receiver used in cognitive radio applications. The three-stage differential ring oscillator is tuned by an array of MOS varactors, which is controlled by a novel staggered voltage offset system for improved tuning linearity. The proposed ring oscillator achieves a measured tuning range from 4.85GHz to 7.15GHz, consuming 4.2mA current from a 1.2V supply voltage. The measured phase noise is -82.5 dBc/Hz at 1MHz offset from an operating frequency of 4.88GHz. The die area of the oscillator core is about 70µm×50µm.
20th European Conference on Circuit Theory and Design, ECCTD 2011, Linkoping, Sweden, Aug. 29-31, 2011; 01/2011
[Show abstract][Hide abstract] ABSTRACT: Compact models for Vertical MOSFETs (VMOSFETs) with channel lengths from 220nm down to 70nm with frame gate and reduced overlap parasitic capacitances were extracted for both EKV3 and BSIM4. Challenging issues emerged from the extraction process due to the device non-idealities such as those related to channel length estimation, absence of “Through” in the de-embedding structure, non availability of a real “Long” device, high level of interface states with a discrete energy level, asymmetrical gate oxide leakage and parasitic inductance on contact metal strips. The BSIM4 approach proved to be the better, for DC and CV modelling, presumably because of the larger set of fitting parameters for modelling short channel effects, body bias, sub-threshold slopes, bias dependent resistances, gate current and overlap capacitances. The cut-off frequency fT data was successfully fitted with the additional layout parasitics simulated. We suggest that the description of methodology and opinions provided here, should prove useful in the modelling of non-standard devices such as those considered for ‘beyond CMOS’ application.
[Show abstract][Hide abstract] ABSTRACT: We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-μm lithography are compared with nonsilicided devices. A source–drain (S/D) activation anneal of 30 s at 1100 ◦C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-μm lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar.
IEEE Transactions on Electron Devices 01/2010; · 2.06 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: We report for the first time a silicidation technology for surround gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for the silicidation. Silicided 120 nm n-channel devices show a 30% improvement in drive current in comparison to non silicided devices, but this is accompanied by a small degradation in sub-threshold slope and DIBL. This problem is solved using a frame gate architecture in which the pillar sidewalls are protected from the silicidation process. Silicided frame gate transistors show a similar increase in drive current without any significant degradation of sub-threshold slope or DIBL. For a 120 nm channel length, silicided frame gate vertical nMOSFETs show a 30% improvement in the drive current with an excellent sub-threshold slope of 78 mV/decade and a DIBL of 30 mV/V. For an 80 nm channel length, a 43% improvement in the drive current is obtained.
Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European; 10/2009
[Show abstract][Hide abstract] ABSTRACT: This paper presents the design of a 10 GHz lumped element band pass filter on standard 130 nm CMOS technology. A series coupled resonator topology is selected due to its advantages over classical low-pass to band-pass filter mapping. A delta-star transformation technique is used in the network synthesis to minimise the impact of stray capacitances, and to avoid the problem of fabricating excessively small coupling capacitors.
Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph.D.; 08/2009
[Show abstract][Hide abstract] ABSTRACT: This paper describes a robust architecture for high speed serial links for embedded SoC applications, implemented to satisfy the 1.5 Gb/s and 3 Gb/s Serial-ATA PHY standards. To meet the primary design requirements of a sub-system that is very tolerant of device variability and is easy to port to smaller nanometre CMOS technologies, a minimum of precision analog functions are used. All digital functions are implemented in rail-to-rail CMOS with maximum use of synthesized library cells. A single fixed frequency low-jitter PLL serves the transmit and receive paths in both modes so that tracking and lock time issues are eliminated. A new oversampling CDR with a simple feed-forward error correction scheme is proposed which relaxes the requirements for the analog front-end as well as for the received signal quality. Measurements show that the error corrector can almost double the tolerance to incoming jitter and to DC offsets in the analog front-end. The design occupies less than 0.4 mm<sup>2</sup> in 90 nm CMOS and consumes 75 mW.
IEEE Journal of Solid-State Circuits 08/2009; · 3.06 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Vertical MOSFETs (VMOSFETs) with channel
lengths down to 100nm and reduced overlap parasitic
capacitance were fabricated using 0.35μm
lithography, with only one extra mask step compared
to standard CMOS technology. EKV modelling
produced reasonable fitting of the DC and AC
characteristics for short channel devices. It is noted
that achieving sufficiently long channels in vertical
pillar devices is difficult and introduces challenges
for accurate and scalable compact modelling. The
measured peak fT was 7.8 GHz and is significantly
limited by high contact resistance and affected by unoptimised
junction formation. The study
comprehensively reveals structure issues that affect
the RF performance. The performance inhibitors have
then been optimised using process and device
simulation. It is demonstrated that fT and fMAX based
on the measurement and numerical simulation, can
reach 30.5GHz, and 41GHz respectively.
[Show abstract][Hide abstract] ABSTRACT: This paper investigates the origins of sub-threshold slope degradation in vertical MOSFETs (v-MOSFETs) due to dry etching of the polysilicon surround gate. Control v-MOSFETs exhibit a degradation of sub-threshold slope as the channel length is reduced from 250 to 100nm, with 100nm transistors having a value of 125 mV/dec and a DIBL of 210 mV/V. The effect of the polysilicon gate etch is investigated using a frame-gate architecture in which the polysilicon gate overlaps the side of the pillar, thereby protecting the channel from etch damage. This device shows no degradation of short channel effects when the channel length is scaled and exhibits a near-ideal sub-threshold slope of 76mV/dec and a DIBL of 33 mV/V at a channel length of 100nm. Gated diode measurements unambiguously demonstrate that this improved sub-threshold slope is due to the elimination of etch damage at the top and bottom of the pillar created during polysilicon gate etch. An alternative method of eliminating dry etch damage is then investigated by optimizing the Fillet Local Oxidation (FILOX). These devices give a sub-threshold slope of 81mV/dec and a DIBL of 25 mV/V at a channel length of 100nm. The improved immunity to dry etch damage is due to the creation of a thick protective oxide at the top and bottom of the pillar during the FILOX process
[Show abstract][Hide abstract] ABSTRACT: This paper describes a dual signal path (MIMO) low power, high performance direct conversion WiBro/WiMAX 802.16 e radio transceiver optimized for mobile applications and for coexistence with co-located cellular and WLAN/Bluetooth systems. The direct-conversion transceiver is designed to be very flexible in respect of biasing and programmability, both to allow power consumption to be traded adaptively versus performance, and flexibility for any changes in the new transmission standard. Signal loopback and transmit power detection techniques are used in conjunction with the baseband modem processor to calibrate transmitter LO leakage and the transceiver and receiver IQ imbalances. The receiver achieves a noise figure (NF) of less than 2.5 dB over an operational frequency range of 2.3-2.7 GHz, and the gain is tunable from 0 dB to 97 dB in 1 dB steps. The maximum linear transmit power is 2.5 dBm and the transmit gain can be digitally controlled over a 75 dB range. The transceiver is fabricated in a 0.25 mum SiGe BiCMOS process and consumes 65/103 mA from a 2.8 V supply in OFDMA Rx/Tx modes, respectively.
IEEE Journal of Solid-State Circuits 09/2008; · 3.06 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: In this work we investigate the series resistances in vertical MOSFETs incorporating the fillet local oxidation (FILOX) structure that serves to reduce the gate to drain/source overlap capacitances. The series resistances are modeled analytically and the important influencing factors, namely gate bias dependence and the asymmetric nature of the device, are identified. We extract by simulation, R<sub>d</sub> and R<sub>s</sub> from devices with different FILOX thicknesses, employing an impedance method often used in RF characterisation. We identify the trade-off whereby thickening the FILOX first causes an increase of the cut-off frequency f<sub>T</sub>, until the on-current I<sub>on</sub> becomes limited by increasing series resistances and f<sub>T</sub> therefore reduces. The results indicate a thickness of 40 nm FILOX for maximum f<sub>T</sub>. We also investigate the influence of process conditions on low series resistances, namely time of rapid thermal annealing RTA and angle of implantation.
Ultimate Integration of Silicon, 2008. ULIS 2008. 9th International Conference on; 04/2008
[Show abstract][Hide abstract] ABSTRACT: In this work we investigate the series resistances
in vertical MOSFETs incorporating the fillet local
oxidation (FILOX) structure that serves to reduce
the gate to drain/source overlap capacitances. The
series resistances are modeled analytically and the
important influencing factors, namely gate bias
dependence and the asymmetric nature of the
device, are identified. We extract by simulation, Rd
and Rs from devices with different FILOX
thicknesses, employing an impedance method
often used in RF characterisation. We identify the
trade-off whereby thickening the FILOX first
causes an increase of the cut-off frequency fT, until
the on-current Ion becomes limited by increasing
series resistances and fT therefore reduces. The
results indicate a thickness of 40nm FILOX for
maximum fT. We also investigate the influence of
process conditions on low series resistances,
namely time of rapid thermal annealing RTA and
angle of implantation.
[Show abstract][Hide abstract] ABSTRACT: This paper describes a 1.5 Gb/s and 3 Gb/s serial PHY architecture aimed at robust operation and ease of porting to smaller technologies. A minimum of precision analogue functions are used, and all digital functions use rail-to-rail CMOS. A single fixed low-jitter PLL serves the transmit and receive paths in both modes, and a new oversampling CDR relaxes the requirements for the analogue front-end as well as for the signal quality. The design occupies
[Show abstract][Hide abstract] ABSTRACT: This paper investigates the asymmetrical characteristics of junctions and their nearby regions in surround gate vertical MOSFETs. The devices have channel lengths defined by implantation, with processes to address some device performance limitations. A ‘junction stop’ process allows optimization of short channel effects by reducing the junction asymmetry but it also induces additional resistance in the top junction. The fillet local oxidation process serves to reduce overlap capacitances however it also induces asymmetry to the top and bottom junction resistances. Non-uniform interface state density down the channel results in asymmetrical subthreshold characteristic. Using a large tilt angle implantation to dope the body can also introduce asymmetry of drain field induced phenomena such as DIBL and impact ionization.
[Show abstract][Hide abstract] ABSTRACT: Micromachined inertial sensors that have been incorporated in sigma-delta force-feedback loops have been proven to improve linearity, dynamic range, and bandwidth, and also provide a direct digital output. Previous work mainly focused on using the sensing element only to form a second-order single-loop sigma-delta modulator (SigmaDeltaM); however, the advantages of higher order single-loop electromechanical SigmaDeltaM have not been fully explored. High-performance inertial sensors require higher signal-to-quantization noise ratio (SQNR). This paper presents topologies for higher order single-loop electromechanical SigmaDeltaM with optimal stable coefficients that lead to a better SQNR. The topologies have good immunity to fabrication tolerances, which was verified by Monte Carlo analysis. The topologies are applicable not only to accelerometers but also to other inertial sensors such as gyroscopes.
IEEE Transactions on Instrumentation and Measurement 11/2007; · 1.71 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This paper describes a dual signal path (MIMO) low power, high performance direct conversion WiBro/WiMAX 802.16e radio transceiver optimized for mobile applications and coexistence with on-board cellular and WLAN/Bluetooth systems. It is fabricated in a SiGe BiCMOS process and achieves a receiver NF of less than 2.5 dB over an operation frequency of 2.3-2.7 GHz. The transmit gain can be digitally tuned over a 75 dB range. The transceiver consumes 65/103 mA at a 2.8 V supply in OFDMA Rx/Tx modes respectively.
[Show abstract][Hide abstract] ABSTRACT: We present a dual-mode receiver for dual-band CDMA 2000 cellular radio, which incorporates an integrated GPS signal path for "E911" emergency call location requirements. The highly integrated zero-IF architecture has separate optimised front-ends, but employs a single shared, reconfigurable baseband path for the two signal bandwidths. The CDMA LO signals are derived from a single external VCO that operates at either twice or 8/9 times the LO frequency at 880 MHz and 1960 MHz respectively, thereby reducing coupling with the transmit path. The circuit is implemented in a 0.25 mum 40 GHz fT BiCMOS process. The chip area is 5 mm<sup>2</sup>; the CDMA CEL/PCS and GPS receivers consume 108/131 mW and 157 mW respectively, using a 2.7 V supply.
Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European; 10/2007
[Show abstract][Hide abstract] ABSTRACT: This work reports on the design of novel closed-loop control systems for the sense mode of a vibratory-rate gyroscope based on a high-order sigma-delta modulator (SigmaDeltaM). A low-pass and two distinctive bandpass topologies are derived, and their advantages discussed. So far, most closed-loop force-feedback control systems for these sensors were based on low-pass SigmaDeltaM's. Usually, the sensing element of a vibratory gyroscope is designed with a high quality factor Q to increase the sensitivity and, hence, can be treated as a mechanical resonator. Furthermore, the output characteristic of vibratory rate gyroscopes is narrowband amplitude-modulated signal. Therefore, a bandpass SigmaDeltaM is a more appropriate control strategy for a vibratory gyroscope than a low-pass SigmaDeltaM. Using a high-order bandpass SigmaDeltaM, the control system can adopt a much lower sampling frequency compared with a low-pass SigmaDeltaM while achieving a similar noise floor for a given oversampling ratio (OSR). In addition, a control system based on a high-order bandpass SigmaDeltaM is superior as it not only greatly shapes the quantization noise, but also alleviates tonal behavior, as is often seen in low-order SigmaDeltaM control systems, and has good immunities to fabrication tolerances and parameter mismatch. These properties are investigated in this study at system level
[Show abstract][Hide abstract] ABSTRACT: The paper presents a novel 6th order continuous-time, force-feedback band-pass sigma-delta modulator control system for the detection mode of micromachined vibratory gyroscopes. Compared with the architecture using a low-pass sigma-delta modulator, this band-pass solution uses a much lower sampling frequency for the sigma-delta modulator and thus reduces the requirement for frequency response of the detection interface and control electronics. In this work, the sigma-delta modulator operates at only four times of mechanical resonant frequency, which allowed its implementation in a continuous-time circuit using discrete electronic components on a PCB; this has the advantage of simple prototyping and can improve the signal anti-aliasing characteristics.