[Show abstract][Hide abstract] ABSTRACT: Resistive random access memory based on TiN/HfOx/TiN has been fabricated, with the stoichiometry of the layer altered through control of atomic layer deposition (ALD) temperature. Sweep and pulsed electrical characteris-tics were extracted before and after gamma irradiation. Monoclinic deposited at 400 did not result in resistive switching. Deposition at 300 and 350 resulted in cubic which switched successfully. Both stoichiometric and sub-oxides result in similar memory characteristics. All devices are shown to be radiation hard up to 10 Mrad(Si), independent of stoichiometry. Index Terms—Atomic layer deposition, hafnium oxide, ionizing radiation, resistive RAM.
[Show abstract][Hide abstract] ABSTRACT: A comparison is made of the behavior of silicon on insulator buried oxides and wet thermal oxides before and after fluorine implantation and irradiation. Before irradiation, the electrical characteristics of the thermal oxide and buried oxide are significantly different. The fluorine implantation in the smart-cut® buried oxide results in a large negative threshold shift due to the trapping of positive charges. These charges are associated with positively charged fluorine ions on implantation and are trapped at pre-existing trap sites, particularly at the bonding interface, and at additional defects caused by the ion implantation damage. This shift is absent in the wet thermal oxide. After Co60 irradiation up to 500 Krad(Si), the negative flatband and threshold voltage shift in the fluorine implanted buried oxide is larger than in the unimplanted buried oxide indicating that any potential positive effect of fluorine on the passivation of interface states is more than offset by the additional trapping sites created during implantation. These results demonstrate that in the design of a transistor utmost care must be taken to prevent any fluorine being implanted into the buried oxide.
[Show abstract][Hide abstract] ABSTRACT: This brief describes an improved current memory circuit aimed at circumventing problems inherent in using a high-voltage double-diffused MOS (DMOS) with CMOS technology. In addition to dealing with the excessive output conductance of a simple cell with cascoding in the familiar way, the circuit addresses the significant drain-gate feedthrough seen in such technologies. A replica bias scheme ensures that the gm of the memory device remains substantially constant notwithstanding the signal current level variations, leading to improved control over charge injection errors. The topology may also be used in conventional small geometry CMOS technology.
Circuits and Systems II: Express Briefs, IEEE Transactions on 06/2013; 60(6):321-325. DOI:10.1109/TCSII.2013.2258251 · 1.23 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This paper presents a novel integrated self-oscillating step-down converter for the fast charging of stacks of large ultracapacitors from a 230V AC mains source. The charger architecture controls both power and current to optimise the charge rate with respect to the limitations imposed by the mains source and the capacitors themselves. The circuit has been fabricated in a 0.35μm bulk medium voltage CMOS, process.
ESSCIRC (ESSCIRC), 2013 Proceedings of the; 01/2013
[Show abstract][Hide abstract] ABSTRACT: An integrated frequency synthesiser is designed and implemented in standard 130 nm complementary metal-oxide semiconductor (CMOS) technology for spectrum monitoring receiver function needed in an associated cognitive radio system. This function demands very wide continuous tuning range albeit with only moderate phase noise performance, although low-power consumption and small die area are high priorities. To meet these unusual specifications, a ring oscillator is used as the frequency source, and a novel high-speed low-power integer-N programmable divider is developed to achieve the tuning range. Using a 25 MHz reference frequency, the ring oscillator-based synthesiser tunes continuously from 5 to 7.3 GHz with 100 MHz steps, maintaining the measured phase noise and reference spur levels below 80.5 dBc/Hz at any frequency offset between 100 kHz and 100 MHz for all output frequencies. The power consumption of the complete frequency synthesiser (excluding the output buffer and the reference crystal oscillator) is 9.98 mW from a 1.2 V supply.
IET Circuits Devices & Systems 11/2012; 6(6):465-472. DOI:10.1049/iet-cds.2012.0014 · 0.52 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Bipolar amplifiers can be biased to give a deep null in third order non-linearity, with the potential for high IP3 amplifier stages. This requires maintaining a precise voltage drop across a small resistive emitter degeneration resistance, whose value is related to kT /q. To make such a scheme practical, the bias must not only take into account the change in kT /q with temperature, but must compensate for variations in the degeneration resistance. In this paper we present a bias technique for IM3 null tracking that can take account of temperature and resistance tolerances, and is also insensitive to the value of the internal emitter resistance. Simulations using a 27 GHz BiCMOS technology indicate that the bias of an amplifier can be maintained over temperature, representative element tolerances, and mismatch such that the IP3 performance is maintained within ±9.5 dBV of the optimum null condition. The technique is applicable for a range of bipolar BiCMOS technologies and is attractive for amplifiers where high IP3 is required with moderate noise figure.
[Show abstract][Hide abstract] ABSTRACT: Two integrated bandpass filters have been designed and fabricated on standard 130 nm CMOS technology. The lumped element, third-order Butterworth bandpass filters at 9.45 and 1.75 GHz are designed for sub-band filtering in a spectrum monitoring receiver function in a future cognitive radio. A series coupled resonator topology is selected and a novel delta-star transformation technique is applied to obtain element values suitable for reliable fabrication on an integrated circuit. Occupying die areas of 780 × 200 μm and 1750 × 500 μm each, the filters achieve insertion losses of 15.6 and 8.6 dB, and band-widths of 1 GHz and 210 MHz, respectively, which are suitable for the chosen spectrum monitor receiver architecture.
[Show abstract][Hide abstract] ABSTRACT: This letter reports a study on the effect of a hydrogen anneal after silicon pillar etch of surround-gate vertical MOSFETs intended for RF applications. A hydrogen anneal at 800°C is shown to give a 30% improvement in the drive current of 120-nm n-channel transistors compared with transistors with out the hydrogen anneal. The value of drive current achieved is 250 μA/μm, which is a record for thick pillar vertical MOSFETs. This improved performance is obtained even though a sacrificial oxidation was performed prior to the hydrogen anneal to smooth the pillar sidewall. The values of subthreshold slope and DIBL are 79 mV/decade and 45 mV/V, respectively, which are significantly better than most values reported in the literature for comparable devices. The H<sub>2</sub> anneal is also shown to decrease the OFF-state leakage current by a factor of three.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a fast and compact charger architecture for ultracapacitors with direct connection to 230V AC mains supply. The charger delivers a DC output current which allows compensation for inductive and other non-ideal behaviour in the EDLC at medium and high frequencies. The internal converter uses self oscillating control circuits which provide a variable switching frequency over a broad range. This allows the circuit to adapt to the variation of the output voltage (0-16.2V) and fluctuations of the mains network, thereby minimizing losses over the whole operating envelope.
20th European Conference on Circuit Theory and Design, ECCTD 2011, Linkoping, Sweden, Aug. 29-31, 2011; 01/2011
[Show abstract][Hide abstract] ABSTRACT: A ring oscillator is designed and implemented on standard 130nm CMOS technology for wide range frequency tuning purpose in a spectrum monitor receiver used in cognitive radio applications. The three-stage differential ring oscillator is tuned by an array of MOS varactors, which is controlled by a novel staggered voltage offset system for improved tuning linearity. The proposed ring oscillator achieves a measured tuning range from 4.85GHz to 7.15GHz, consuming 4.2mA current from a 1.2V supply voltage. The measured phase noise is -82.5 dBc/Hz at 1MHz offset from an operating frequency of 4.88GHz. The die area of the oscillator core is about 70µm×50µm.
20th European Conference on Circuit Theory and Design, ECCTD 2011, Linkoping, Sweden, Aug. 29-31, 2011; 01/2011
[Show abstract][Hide abstract] ABSTRACT: We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-μm lithography are compared with nonsilicided devices. A source–drain (S/D) activation anneal of 30 s at 1100 ◦C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-μm lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar.
IEEE Transactions on Electron Devices 12/2010; 57(12). DOI:10.1109/TED.2010.2082293 · 2.47 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Compact models for Vertical MOSFETs (VMOSFETs) with channel lengths from 220nm down to 70nm with frame gate and reduced overlap parasitic capacitances were extracted for both EKV3 and BSIM4. Challenging issues emerged from the extraction process due to the device non-idealities such as those related to channel length estimation, absence of “Through” in the de-embedding structure, non availability of a real “Long” device, high level of interface states with a discrete energy level, asymmetrical gate oxide leakage and parasitic inductance on contact metal strips. The BSIM4 approach proved to be the better, for DC and CV modelling, presumably because of the larger set of fitting parameters for modelling short channel effects, body bias, sub-threshold slopes, bias dependent resistances, gate current and overlap capacitances. The cut-off frequency fT data was successfully fitted with the additional layout parasitics simulated. We suggest that the description of methodology and opinions provided here, should prove useful in the modelling of non-standard devices such as those considered for ‘beyond CMOS’ application.
[Show abstract][Hide abstract] ABSTRACT: We report for the first time a silicidation technology for surround gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for the silicidation. Silicided 120 nm n-channel devices show a 30% improvement in drive current in comparison to non silicided devices, but this is accompanied by a small degradation in sub-threshold slope and DIBL. This problem is solved using a frame gate architecture in which the pillar sidewalls are protected from the silicidation process. Silicided frame gate transistors show a similar increase in drive current without any significant degradation of sub-threshold slope or DIBL. For a 120 nm channel length, silicided frame gate vertical nMOSFETs show a 30% improvement in the drive current with an excellent sub-threshold slope of 78 mV/decade and a DIBL of 30 mV/V. For an 80 nm channel length, a 43% improvement in the drive current is obtained.
Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European; 10/2009
[Show abstract][Hide abstract] ABSTRACT: This paper presents the design of a 10 GHz lumped element band pass filter on standard 130 nm CMOS technology. A series coupled resonator topology is selected due to its advantages over classical low-pass to band-pass filter mapping. A delta-star transformation technique is used in the network synthesis to minimise the impact of stray capacitances, and to avoid the problem of fabricating excessively small coupling capacitors.
Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph.D.; 08/2009
[Show abstract][Hide abstract] ABSTRACT: This paper describes a robust architecture for high speed serial links for embedded SoC applications, implemented to satisfy the 1.5 Gb/s and 3 Gb/s Serial-ATA PHY standards. To meet the primary design requirements of a sub-system that is very tolerant of device variability and is easy to port to smaller nanometre CMOS technologies, a minimum of precision analog functions are used. All digital functions are implemented in rail-to-rail CMOS with maximum use of synthesized library cells. A single fixed frequency low-jitter PLL serves the transmit and receive paths in both modes so that tracking and lock time issues are eliminated. A new oversampling CDR with a simple feed-forward error correction scheme is proposed which relaxes the requirements for the analog front-end as well as for the received signal quality. Measurements show that the error corrector can almost double the tolerance to incoming jitter and to DC offsets in the analog front-end. The design occupies less than 0.4 mm<sup>2</sup> in 90 nm CMOS and consumes 75 mW.
[Show abstract][Hide abstract] ABSTRACT: This paper investigates the origins of sub-threshold slope degradation in vertical MOSFETs (v-MOSFETs) due to dry etching of the polysilicon surround gate. Control v-MOSFETs exhibit a degradation of sub-threshold slope as the channel length is reduced from 250 to 100nm, with 100nm transistors having a value of 125 mV/dec and a DIBL of 210 mV/V. The effect of the polysilicon gate etch is investigated using a frame-gate architecture in which the polysilicon gate overlaps the side of the pillar, thereby protecting the channel from etch damage. This device shows no degradation of short channel effects when the channel length is scaled and exhibits a near-ideal sub-threshold slope of 76mV/dec and a DIBL of 33 mV/V at a channel length of 100nm. Gated diode measurements unambiguously demonstrate that this improved sub-threshold slope is due to the elimination of etch damage at the top and bottom of the pillar created during polysilicon gate etch. An alternative method of eliminating dry etch damage is then investigated by optimizing the Fillet Local Oxidation (FILOX). These devices give a sub-threshold slope of 81mV/dec and a DIBL of 25 mV/V at a channel length of 100nm. The improved immunity to dry etch damage is due to the creation of a thick protective oxide at the top and bottom of the pillar during the FILOX process
[Show abstract][Hide abstract] ABSTRACT: Vertical MOSFETs (VMOSFETs) with channel
lengths down to 100nm and reduced overlap parasitic
capacitance were fabricated using 0.35μm
lithography, with only one extra mask step compared
to standard CMOS technology. EKV modelling
produced reasonable fitting of the DC and AC
characteristics for short channel devices. It is noted
that achieving sufficiently long channels in vertical
pillar devices is difficult and introduces challenges
for accurate and scalable compact modelling. The
measured peak fT was 7.8 GHz and is significantly
limited by high contact resistance and affected by unoptimised
junction formation. The study
comprehensively reveals structure issues that affect
the RF performance. The performance inhibitors have
then been optimised using process and device
simulation. It is demonstrated that fT and fMAX based
on the measurement and numerical simulation, can
reach 30.5GHz, and 41GHz respectively.
[Show abstract][Hide abstract] ABSTRACT: This paper describes a dual signal path (MIMO) low power, high performance direct conversion WiBro/WiMAX 802.16 e radio transceiver optimized for mobile applications and for coexistence with co-located cellular and WLAN/Bluetooth systems. The direct-conversion transceiver is designed to be very flexible in respect of biasing and programmability, both to allow power consumption to be traded adaptively versus performance, and flexibility for any changes in the new transmission standard. Signal loopback and transmit power detection techniques are used in conjunction with the baseband modem processor to calibrate transmitter LO leakage and the transceiver and receiver IQ imbalances. The receiver achieves a noise figure (NF) of less than 2.5 dB over an operational frequency range of 2.3-2.7 GHz, and the gain is tunable from 0 dB to 97 dB in 1 dB steps. The maximum linear transmit power is 2.5 dBm and the transmit gain can be digitally controlled over a 75 dB range. The transceiver is fabricated in a 0.25 mum SiGe BiCMOS process and consumes 65/103 mA from a 2.8 V supply in OFDMA Rx/Tx modes, respectively.
[Show abstract][Hide abstract] ABSTRACT: In this work we investigate the series resistances in vertical MOSFETs incorporating the fillet local oxidation (FILOX) structure that serves to reduce the gate to drain/source overlap capacitances. The series resistances are modeled analytically and the important influencing factors, namely gate bias dependence and the asymmetric nature of the device, are identified. We extract by simulation, R<sub>d</sub> and R<sub>s</sub> from devices with different FILOX thicknesses, employing an impedance method often used in RF characterisation. We identify the trade-off whereby thickening the FILOX first causes an increase of the cut-off frequency f<sub>T</sub>, until the on-current I<sub>on</sub> becomes limited by increasing series resistances and f<sub>T</sub> therefore reduces. The results indicate a thickness of 40 nm FILOX for maximum f<sub>T</sub>. We also investigate the influence of process conditions on low series resistances, namely time of rapid thermal annealing RTA and angle of implantation.
Ultimate Integration of Silicon, 2008. ULIS 2008. 9th International Conference on; 04/2008
[Show abstract][Hide abstract] ABSTRACT: This paper describes a 1.5 Gb/s and 3 Gb/s serial PHY architecture aimed at robust operation and ease of porting to smaller technologies. A minimum of precision analogue functions are used, and all digital functions use rail-to-rail CMOS. A single fixed low-jitter PLL serves the transmit and receive paths in both modes, and a new oversampling CDR relaxes the requirements for the analogue front-end as well as for the signal quality. The design occupies