Kozo KINOSHITA

Publications (67)0.56 Total impact

• Article: A statistical error model for image sensors and its testing

  Hideyuki Ichihara, Toshimasa Kuchii, Masaaki Yamadate, Hideaki Sakaguchi, Hiroshi Uemura, Kozo Kinoshita
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  ABSTRACT: Since images obtained from image sensor devices are commonly tested by performing a manual inspection or by means of procedures that involve large amounts of image processing, the growth in testing costs as the size of such devices increases poses a significant problem. Several approaches to automating the testing process have been proposed with a view to reducing testing costs but trial and error is needed to set the parameters required by such test procedures. In this paper we propose an error model for images taken by image sensor devices that can perform a quantitative evaluation with a small number of free parameters. Image quality testing can be performed relatively easily using this model since it replaces a previously ambiguous error model by one that can be determined uniquely. In addition, since the proposed error model is defined statistically in terms of the brightness levels of pixels in each of the individual images, even if there are individual differences between the image sensor devices, these have no influence on the testing procedure. Experimental results demonstrate that an image quality testing based on the proposed error model has the same level of accuracy as manual inspections performed by an experienced technician. © 2007 Wiley Periodicals, Inc. Syst Comp Jpn, 38(11): 1– 11, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.20804
  Systems and Computers in Japan 07/2007; 38(11):1 - 11.
• Article: Stuck‐open faults test generation for cmos combinational circuits

  Seiji Kajihara, Noriyoshi Itazaki, Kozo Kinoshita
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  ABSTRACT: This paper proposes a stuck-open test generation system which generates test patterns with high fault coverage for single stuck-open faults in CMOS combinational circuits. In the proposed method, although the stuck-open faults are treated at switch level in each cell consisting of CMOS logic gates, test patterns for the overall circuit are generated at gate level using a path sensitization method. To reduce the number of test patterns, a gate level circuit is partitioned into subcircuits. Also, heuristics are introduced to select a sensitizing path dynamically such that a pair of test vectors could detect many more faults. Finally, some results are presented about test pattern generation for combinational benchmark circuits.
  Systems and Computers in Japan 03/2007; 22(9):33 - 42.
• Article: A Novel ATPG Method for Capture Power Reduction during Scan Testing.

  Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
  IEICE Transactions. 01/2007; 90-D:1398-1405.
• Conference Proceeding: A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.

  Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
  24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA; 01/2006
• Source

  Available from: jcst.ict.ac.cn

  Article: Fault Diagnosis of Physical Defects Using Unknown Behavior Model

  Xiao-Qing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
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  ABSTRACT: A new fault model, called the X-fault model, is proposed for fault diagnosis of physical defects with unknown behaviors by using X symbols. An efficient X-fault simulation method and an efficient X-fault diagnostic reasoning method are presented. Fault diagnosis based on the X-fault model can improve the accuracy of failure analysis for a wide range of physical defects in complex and deep submicron integrated circuits.
  Journal of Computer Science and Technology 02/2005; 20(2):187-194. · 0.56 Impact Factor
• Article: On Design for I

  Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
  IEICE Transactions. 01/2005; 88-D:703-710.
• Conference Proceeding: Low-capture-power test generation for scan-based at-speed testing.

  Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
  Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005; 01/2005
• Conference Proceeding: On Low-Capture-Power Test Generation for Scan Testing.

  Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
  23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA; 01/2005
• Article: Fault Diagnosis of Physical Defects Using Unknown Behavior Model.

  Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
  J. Comput. Sci. Technol. 01/2005; 20:187-194.
• Conference Proceeding: On per-test fault diagnosis using the X-fault model.

  Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
  2004 International Conference on Computer-Aided Design (ICCAD'04), November 7-11, 2004, San Jose, CA, USA; 01/2004
• Conference Proceeding: Fault Diagnosis for Physical Defects of Unknown Behaviors.

  Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
  12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China; 01/2003
• Conference Proceeding: On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.

  Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita
  Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002; 01/2002
• Source

  Available from: york.ac.uk

  Conference Proceeding: Fault models and test generation for IDDQ testing: embedded tutorial.

  Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
  Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan; 01/2000
• Article: Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.

  Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
  J. Electronic Testing. 01/2000; 16:443-451.
• Conference Proceeding: Test Transformation to Improve Compaction by Statistical Encoding.

  Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
  13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India; 01/2000
• Article: Static test compaction for IDDQ testing of bridging faults in sequential circuits.

  Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita
  Systems and Computers in Japan. 01/2000; 31:41-50.
• Conference Proceeding: Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits.

  Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
  12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India; 01/1999
• Conference Proceeding: Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits.

  Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
  8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China; 01/1999
• Conference Proceeding: Design for Diagnosability of CMOS Circuits.

  Xiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
  7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore; 01/1998
• Conference Proceeding: Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits.

  Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
  7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore; 01/1998