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ABSTRACT: Since images obtained from image sensor devices are commonly tested by performing a manual inspection or by means of procedures that involve large amounts of image processing, the growth in testing costs as the size of such devices increases poses a significant problem. Several approaches to automating the testing process have been proposed with a view to reducing testing costs but trial and error is needed to set the parameters required by such test procedures. In this paper we propose an error model for images taken by image sensor devices that can perform a quantitative evaluation with a small number of free parameters. Image quality testing can be performed relatively easily using this model since it replaces a previously ambiguous error model by one that can be determined uniquely. In addition, since the proposed error model is defined statistically in terms of the brightness levels of pixels in each of the individual images, even if there are individual differences between the image sensor devices, these have no influence on the testing procedure. Experimental results demonstrate that an image quality testing based on the proposed error model has the same level of accuracy as manual inspections performed by an experienced technician. © 2007 Wiley Periodicals, Inc. Syst Comp Jpn, 38(11): 1– 11, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.20804
Systems and Computers in Japan 07/2007; 38(11):1 - 11.
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ABSTRACT: This paper proposes a stuck-open test generation system which generates test patterns with high fault coverage for single stuck-open faults in CMOS combinational circuits. In the proposed method, although the stuck-open faults are treated at switch level in each cell consisting of CMOS logic gates, test patterns for the overall circuit are generated at gate level using a path sensitization method. To reduce the number of test patterns, a gate level circuit is partitioned into subcircuits. Also, heuristics are introduced to select a sensitizing path dynamically such that a pair of test vectors could detect many more faults. Finally, some results are presented about test pattern generation for combinational benchmark circuits.
Systems and Computers in Japan 03/2007; 22(9):33 - 42.
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IEICE Transactions. 01/2007; 90-D:1398-1405.
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24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA; 01/2006
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ABSTRACT: A new fault model, called the X-fault model, is proposed for fault diagnosis of physical defects with unknown behaviors by using X symbols. An efficient X-fault simulation method and an efficient X-fault diagnostic reasoning method are presented. Fault diagnosis based on the X-fault model can improve the accuracy of failure analysis for a wide range of physical defects in complex and deep submicron integrated circuits.
Journal of Computer Science and Technology 02/2005; 20(2):187-194. · 0.56 Impact Factor
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IEICE Transactions. 01/2005; 88-D:703-710.
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Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005; 01/2005
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23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA; 01/2005
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J. Comput. Sci. Technol. 01/2005; 20:187-194.
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2004 International Conference on Computer-Aided Design (ICCAD'04), November 7-11, 2004, San Jose, CA, USA; 01/2004
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12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China; 01/2003
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Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002; 01/2002
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Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan; 01/2000
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J. Electronic Testing. 01/2000; 16:443-451.
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13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India; 01/2000
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Systems and Computers in Japan. 01/2000; 31:41-50.
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12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India; 01/1999
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8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China; 01/1999
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7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore; 01/1998
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7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore; 01/1998