E. Merlo

Institute of Electrical and Electronics Engineers, Washington, Washington, D.C., United States

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Publications (7)0 Total impact

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    ABSTRACT: A single-chip direct digital frequency synthesizer with hardware efficient phase-to-amplitude mapping and an integrated DAC achieves over 50dB SFDR in full-Nyquist band at 1.7GHz clock frequency for synthesized output signals up to 850MHz. The IC is implemented in a 0.35 μm SiGe BiCMOS process and occupies an area of 4.8×5.0mm<sup>2</sup>. Power efficiency is 1.76mW/MHz at 3V.
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International; 03/2005
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    Edward MERLO, Kwang-Hyun BAEK
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    ABSTRACT: This paper presents high-speed low-power small-area accumulator designs to be used in DDFS systems. To reduce the Numerically Controlled Oscillator (NCO) design complexity and size, only the most significant bits of the accumulator drive the phase to amplitude mapping block. Those bits need to be updated on every sampling clock, while the least significant bits of the accumulator are not visible to the rest of the DDFS design and can be updated less frequently, which motivated the development of new accumulator designs. Without performance degradation, the proposed designs relieve constraints in implementation, and hence they can be employed for GHz-range DDFS, reduce power consumption up to 82&percnt; compared to standard accumulator design, and minimize chip area. For further power reduction, the proposed designs place the phase modulation adder at the front of the accumulator.
    01/2005;
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    ABSTRACT: This paper presents a 1-GS/s, 12-bit SiGe BiCMOS D/A converter combined with high-speed low-spurious BiCMOS current switches and an efficient calibration method for current mismatch. Experimental results show a reduction in INL and DNL errors from +35.5/-62.2 LSB to +4.1/-3.4 LSB and from +8.1/-10.3 LSB to +6.2/-1.2 LSB, respectively, after calibration. SFDR performance is 72.3 dBc at output frequency of 1.82 MHz and 50.0 dBc at output frequency of 334.39 MHz, when the sampling clock frequency is 1 GHz. Power consumption is about 950 mW at 100.48MHz output frequency and -3.3 V power supply.
    Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on; 06/2003
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    ABSTRACT: This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches the GHz range. A robust FIFO built in the D/A converter can absorb data-dependent input timing variance, the worst-case margin of which is ±1.5×T<sub>CLK</sub>. Distributed LCR transmission line models for on-chip interconnects produce more accurate simulation results at 1 GHz clock frequency than lumped models. Measurement results verify the accuracy of the interconnect models. Behavioral modeling methodology is also presented in this paper for optimized D/A converter design.
    Mixed-Signal Design, 2003. Southwest Symposium on; 03/2003
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    ABSTRACT: A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section of the accumulator that is not used to address the phase to amplitude mapping block thus reducing area, constraints in implementation, and up to 82% in power consumption compared to standard designs.
    Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003; 01/2003
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    Edward Merlo, Kwang-Hyun Baek
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    ABSTRACT: A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section of the accumulator that is not used to address the phase to amplitude mapping block thus reducing area, constraints in implementation, and up to 82% in power consumption compared to standard designs.
    01/2003;
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    ABSTRACT: A new split accumulator architecture to be used in direct digital frequency synthesizer (DDS) systems is presented in this paper. This new design takes into consideration that only part of the accumulator output is used to address the sine wave mapping. The most significant bits of the accumulator drive the mapping block and need to be updated on every sampling clock, while the least significant bits are not visible to the rest of the design and can be updated less frequently. Also the phase modulation adder is moved to the front of the accumulator. Benefits of the proposed architecture are fewer constraints in implementation, reduced power consumption of 40% (estimation) compared to standard approaches, and less area with no degradation in terms of spurious-free dynamic range (SFDR) performance.
    ASIC/SOC Conference, 2002. 15th Annual IEEE International; 10/2002