A.K. Majhi

NXP Semiconductors, Eindhoven, North Brabant, Netherlands

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Publications (21)2.31 Total impact

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    ABSTRACT: Power supply noise (PSN) has become a critical issue during high-quality at-speed testing. Discrepancies between the circuit's switching activity during functional and test mode can cause overtesting and lead to yield loss. Alternatively, reduced PSN effects around critical paths can result in undertesting the chip, causing test escapes. To achieve a high-quality at-speed test, it is necessary to solve these problems simultaneously. Our previous work introduced a noise index model (NIM), which can be used to predict the mismatch between expected and real path delays. This paper quantitatively investigates and compares NIM values for critical paths during functional and test mode. We then propose a test pattern modification method that harnesses the NIM. The method fills a subset of the don't care bits in partially specified test vectors such that the worst observed functional NIM for the targeted critical path is replicated during test mode.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 01/2012; 31(5):809-813. · 1.09 Impact Factor
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    ABSTRACT: As CMOS technology continues to scale, the accurate prediction of silicon timing through the use of pre-silicon modeling and analysis has become especially difficult. These timing mismatches are important because they make it hard to accurately design circuits that meet timing specifications at first-silicon. Among all the parameters leading to the timing discrepancy between simulation and silicon, this paper studies the effect of dynamic IR-drop on the delay of a path. We propose a noise index model, NIM, which can be used to predict the mismatch between expected and real path delays. The noise index considers both the proximity of switching activity to the path and physical characteristics of the design. To evaluate the method, we performed silicon measurements on randomly selected paths from an industrial 65nm design and compared these with Spice simulations. We show that a very strong correlation exists between the noise index model and the deviations between simulations and silicon measurements.
    Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010; 01/2010
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    ABSTRACT: The usage of more advanced, less mature processes during manufacturing of semiconductor devices has increased the need for performing unconventional types of testing, like temperature-testing, in order to maintain the same high quality levels. However, performing temperature-testing is costly. This paper proposes a viable low-cost alternative to temperature testing that quantifies the impact of temperature variations on the test quality and also determines optimal test conditions. The test flow proposed is empirically validated on an industrial-standard die. The results obtained show that majority of the defects that were originally detected by temperature-testing are also detected by the proposed test flow, thereby reducing the dependence on temperature testing to achieve zero-defect quality. Details of an interesting defect behavior at cold test conditions is also presented.
    VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010; 01/2010
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    ABSTRACT: Volume Yield Diagnostics (VYD) is crucial to diagnose critical systematic yield issues from the reports obtained by testing thousands of chips. This paper presents an efficient clustering technique for VYD that has been shown to work successfully both in the simulation environment as well as on real industrial failure data.
    VLSI Design, 2009 22nd International Conference on; 02/2009
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    ABSTRACT: Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this class of defect becomes relevant for present and future technologies. Bridging defects cause two additional current components, the bridge and the downstream current. This work presents the effect of the downstream current on current signatures and its impact on the diagnosis of such defects. We demonstrate that the impact of downstream current is minimized at low power supply (VDD) values. Therefore, current measurements at low power supply voltages are proposed to enhance bridge diagnosis. Experimental evidence of this behaviour is presented for real devices. Furthermore, current signatures measured at VVLV are used for the diagnosis of fifteen failing 0.18\mu m technology devices, which are demonstrated to contain a bridging defect.
    VLSI Test Symposium, IEEE. 01/2007;
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    ABSTRACT: A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.
    VLSI Test Symposium, IEEE. 01/2007;
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    ABSTRACT: Excessive power supply noise can affect path delay and cause overkill during delay test. This paper presents low-cost noise models for fast power supply noise analysis and timing analysis considering noise impact. Our prior work only considered array-bond chips. This work proposes a noise analysis methodology that can be applied to wire-bond chips as well as array-bond chips. Experiments were performed on an industrial design. Silicon results show as much as a 15% delay variation due to different don't care fill approaches. The power supply noise impact on delay must be taken into account when delay tests are applied
    2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006; 01/2006
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    ABSTRACT: This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low voltage, high voltage and at-speed testing show the need of the stress conditions for high quality products; i.e., low defect-per-million (DPM) level, which is driving the semiconductor market today. The above test conditions have been validated to screen out bad devices on real silicon (a test-chip) built on CMOS 0.18 μm technology. The IFA (inductive fault analysis) based simulation technique leads to an efficient fault coverage and DPM estimator, which helps the customers upfront to make decisions on test algorithm implementations under different stress conditions in order to reduce the number of test escapes.
    Design, Automation and Test in Europe, 2005. Proceedings; 04/2005
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    ABSTRACT: This work proposes an effective method for applying fine-delay fault testing in order to improve defect coverage of especially resistive opens. The method is based on grouping conventional delay-fault patterns into sets of almost equal-length paths. This narrows the overall path length distribution and allows running the pattern sets at a higher speed, thus enabling the detection of small delay faults. These small delay faults are otherwise undetectable because they are masked by longer paths. A requirement for this method is to have hazard-free paths. To obtain these (almost) hazard-free paths we use a fast and simple postprocessing step that filters out paths with hazards. The experimental data shows the effectiveness and the necessity of this filtering process.
    Test Conference, 2004. Proceedings. ITC 2004. International; 11/2004
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    M. Azimane, A.K. Majhi
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    ABSTRACT: Intra-gate resistive open defects not only cause sequential behaviour in CMOS memory address decoders, but also lead to delay behaviour. This paper evaluates the fault coverage of the resistive open defects in the memory address decoders. It shows that both the strong and the weak open defects are not completely covered by applying the well-known March tests and special test pattern sequences published in the literature. We demonstrate that the fault coverage is increased by varying the duty cycle of the internal clock of the address decoder. For the self-timed memories, we introduce a simple DFT technique to control the duty cycle of the internal clock which activates/deactivates the word lines. Using defect-oriented test, we also created a fault dictionary based on the defect location, transistor types, the terminal name and also the faulty behaviour. The fault dictionary in combination with the bit-map fail data will facilitate the localization of the open defects.
    VLSI Test Symposium, 2004. Proceedings. 22nd IEEE; 05/2004
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    ABSTRACT: Defects due to process-design interaction have a sys- tematic nature. Therefore they can have a profound im- pact on yield. The capability to detect (and correct) them is a requirement to continue to follow Moore's law. Most of the systematic defects are detected during the process development. These defects are detectable with test struc- tures or visual inspection tools. However some process marginalities will only show-up in the topology of 'real' designs. Moreover, these defects are often not detectable with stuck-at testing. We show two examples of process re- lated defects which could only be detected with more ad- vanced test methods such as transition fault testing and low voltage testing. To correct systematic problems, how- ever, one should not only have the capability to detect de- fects but also to identify them. Our examples show that other tests would have been far more sensitive in detect- ing systematic issues. Therefore the detection of systemat- ic defects gives new requirements to test suites and can only be achieved with a shift in the position of manufac- turing test.
    01/2004;
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    ABSTRACT: The known methods of transition fault diagnosis usually suffer from the drawback of many candidates. The method presented in this paper aims at reducing the number of suspects. The transition fault patterns were generated by Philips in-house ATPG tool and applied on the tester. The fail information from tester was subjected to fault diagnosis resulting in a small list of faulty candidates. We then injected the delay faults into the golden netlist of the test chip and confirmed through simulation whether or not their behavior matched with the tester results. Upon successful matching, we proceeded with the selection of few testable paths through the suspect faulty node and created corresponding path delay patterns using the path delay ATPG (a prototype at the University of Bremen, developed in cooperation with Philips Semiconductors GmbH, Hamburg). Finally, we verified those path delay patterns on the tester to increase the confidence level of the diagnosis method The experimental results show the effectiveness of our novel approach for improving diagnostic resolution.
    VLSI Test Symposium, 2003. Proceedings. 21st; 01/2003
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    ABSTRACT: We propose a new coverage metric for delay fault tests. The coverage is measured for each line with a rising and a falling transition, but the test criterion differs from that of the slow-to-rise and slow-to-fall transition faults. A line is tested by a line delay test, which is a robust path delay test for the longest sensitizable path producing a given transition on the target line. Thus, the test criterion resembles path delay test and not the gate or transition delay test. Yet, the maximum number of tests (or faults) is limited to twice the number of lines. In a two-pass test-generation procedure, we first attempt delay tests for a minimal set of longest paths for all lines. Fault simulation is used to determine the coverage metric. For uncovered lines, in the second pass, several paths of decreasing lengths are targeted. We give results for several benchmark circuits.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11/2000; · 1.22 Impact Factor
  • S. Balajee, A.K. Majhi
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    ABSTRACT: One of the major requirements for testing VLSI devices is the validation of its timing specifications. Timing specifications would typically include frequency, propagation delays, minimum pulse width, phase offsets, setup time and hold time measurements. Although parametric specifications may exist for a nominal speed (frequency) of operation of the digital device, it may be necessary to characterize the device under test (DUT) to determine the highest operating frequency of the DUT and the required environmental parameters to run at the highest frequency. Characterization involves measurement of setup time, hold time and pulse width of the signals. In this paper, we have presented an automated AC (timing) characterization flow for digital circuit testing. We have recommended a STIL (Standard Tester Interface Language) like syntax for the timing tests. Various timing data (setup and hold time, propagation delay etc.) are measured in the first pass of the characterization process and are automatically back annotated to the timing test flow to reduce the total test cycle time. The approach will also help in finding the maximum operating frequency of the DUT and speed binning (i.e., sorting the devices based on their operating frequency)
    VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on; 02/1998
  • A.K. Majhi, V.D. Agrawal
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    ABSTRACT: Failures that cause logic circuits to malfunction at the desired clock rate and thus violate timing specifications are currently receiving much attention. Such failures are modeled as delay faults. They facilitate delay testing. The use of delay fault models in VLSI test generation is very likely to gain industry acceptance in the near future. In this paper, we review delay fault models, discuss their classifications and examine fault coverage metrics that have been proposed in the recent literature. A comparison between delay fault models, namely, gate delay, transition, path delay, line delay and segment delay faults, shows their benefits and limitations. Various classifications of the path delay fault model, that have received the most attention in recent years, are reviewed. We believe an understanding of delay fault models is essential in today's VLSI design and test environment
    VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on; 02/1998
  • Conference Paper: Mixed-signal test
    A.K. Majhi, V.D. Agrawal
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    ABSTRACT: The test process for analog circuits currently focuses on performance verification, generally known as functional testing. For many classes of analog circuits, there are already well-known and accepted functional tests. However, the test development time and test set application time are too long for today's circuits. For new products, short product cycles and time-to-market are critical considerations. Test development time has two main factors: the presence of noise and a lack of powerful tools, models and practices. Besides, functional testing has been reported to fail in many system applications. Today, more often than before, there is a consensus that structural testing is a viable solution. A brief survey of the current trends and challenges in mixed-signal testing is given in this paper
    VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on; 02/1998
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    ABSTRACT: We propose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and a falling transition. However, the test criterion is different from that of the slow-to-rise and slow-to-fall transition faults. The test, called “line delay test”, is a path delay test for the longest sensitizable path producing a given transition on the target line. The maximum number of tests (and faults) is limited to twice the number of lines. However, the line delay test criterion resembles path delay test and not the gate or transition delay test. Using a two-pass test generation procedure, we begin with a minimal set of longest paths covering all lines and generate tests for them. Fault simulation is used to determine the coverage metric. For uncovered lines, in the second pass, several paths of decreasing length are targeted. We present a theorem stating that a redundant stuck-at fault makes all path delay faults involving the faulty line untestable for either a rising or falling transition depending on the type of the stuck-at fault. The use of this theorem considerably reduces the effort of delay test generation. We give results on benchmark circuits
    VLSI Design, 1996. Proceedings., Ninth International Conference on; 02/1996
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    Ananta K Majhi, James Jacob, Lalit M Patnaik
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    ABSTRACT: A novel path delay fault simulator for combinational logic circuits which is capable of detecting both robust and nonrobust paths is presented. Particular emphasis has been given for the use of binary logic rather than the multiple-valued logic as used in the existing simulators which contributes to the reduction of the overall complexity of the algorithm. A rule based approach has been developed which identifies all robust and nonrobust paths tested by a two-pattern test <V1,V2>, while backtracing from the POs to PIs in a depth-first manner. Rules are also given to find probable glitches and to determine how they propagate through the circuit, which enables the identification of nonrobust paths. Experimental results on several ISCAS'85 benchmark circuits demonstrate the efficiency of the algorithm.
    VLSI Design 01/1996;
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    ABSTRACT: The new test pattern generation system for path delay faults in combinational logic circuits considers robust and nonrobust tests, simultaneously. Once a robust test is obtained for a path with a given transition, another test for the same path with the opposite transition is immediately derived with a small extra effort. To facilitate the simultaneous consideration of robust and nonrobust tests, we derive a new nine-value logic system. An efficient multiple backtrace procedure satisfies test generation objectives. We also use a path selection method which covers all lines in the logic circuit by the longest and the shortest possible paths through them. A fault simulator in the system gives information on robust and nonrobust detection of faults either from a given target set or all path faults. Experimental results on ISCAS'85 and ISCAS'89 benchmark circuits substantiate the efficiency of our algorithm in comparison to other published results
    VLSI Design, 1995., Proceedings of the 8th International Conference on; 02/1995
  • Ananta K. Majhi, L.M. Patnaik, Srilata Raman
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    ABSTRACT: Multichip Modules (MCMs) is a packaging technology gaining importance, because it reduces the interconnect delays across chips, by bringing the interconnect delays closer in magnitude to the on-chip delays. The problem here is to partition a circuit across multiple chips, producing MCMs. Partitioning is a combinatorial optimization problem. One of the methods to solve the problem is by the use of Genetic Algorithms (GAs), which are based on genetics. GAs can be used to solve both combinatorial as well as functional optimization problems. This paper solves the problem of partitioning using the GA approach. The performance of GAs is compared with that of Simulated Annealing (SA), by executing the algorithms on three benchmark circuits. The effect of varying the parameters of the algorithm on the performance of GAs is studied.
    Microprocessing and Microprogramming. 01/1995;

Publication Stats

297 Citations
2.31 Total Impact Points

Institutions

  • 2007–2010
    • NXP Semiconductors
      Eindhoven, North Brabant, Netherlands
  • 2009
    • Indian Institute of Technology Madras
      Chennai, Tamil Nādu, India
  • 1998
    • Mentor Graphics
      Wilsonville, Oregon, United States
  • 1995–1996
    • Indian Institute of Science
      • Department of Electrical and Communication Engineering
      Bengalore, State of Karnataka, India
    • University of Illinois, Urbana-Champaign
      Urbana, Illinois, United States