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ABSTRACT: This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors’ knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects. Peer reviewed
CICYT- TEC2005-07985-C03-02.
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ABSTRACT: A nonlinear auto-regressive moving average (ARMA) structure capable of compensating nonlinear memory effects in RF power amplifiers is here presented. Results on the linearity improvement, in both in-band and out-of-band distortion compensation, achieved by this baseband digital predistorter are provided. Moreover, a study on this nonlinear ARMA system stability is also reported.
CICYT- TEC2005-07985-C03-02.
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ABSTRACT: This paper presents the design of an adaptive Digital Predistorter (DPD) for Power Amplifier (PA) linearization whoseimplementation and real time adaptation can be fully performed in a Field Programmable Gate Array (FPGA). The distinctive characteristic of this adaptive DPD is its straightforward deduction from a Nonlinear Auto Regressive Moving Average (NARMA) PA model and the possibility to be completely implemented in a FPGA without the need of an additional digital signal processor performing the DPD adaptation. The adaptive DPD presents a NARMA structure that can be implemented by means of Look-Up Tables (LUTs). This configuration results in a Multi-LUT implementation where LUT contents are directly updated by means of an LMS algorithm. Details on the internal adaptive DPD organization as well as its linearization capabilities are provided, taking into account memory effects compensation.
CICYT- TEC2005-07985-C03-02.
