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IEICE Transactions. 01/2011; 94-A:1201-1209.
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IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2010; 29:250-260.
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IEICE Transactions. 01/2009; 92-A:2531-2539.
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Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007; 01/2007
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ABSTRACT: Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance C<sub>eff</sub> concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to C<sub>eff</sub> and RC-pi are not equal was not considered. With the progress of IC process technology, its influence on static timing analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation
Communications, Circuits and Systems Proceedings, 2006 International Conference on; 07/2006
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IEICE Transactions. 01/2006; 89-A:847-855.
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IEICE Transactions. 01/2006; 89-A:856-864.
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IEICE Transactions. 01/2006; 89-A:840-846.
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6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA; 01/2005
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International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan; 01/2005
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IEICE Transactions. 01/2005; 88-A:3367-3374.
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6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA; 01/2005
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IEICE Transactions. 01/2005; 88-A:3412-3420.
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IEICE Transactions. 01/2005; 88-A:3471-3478.
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IEICE Transactions. 01/2005; 88-A:3453-3462.
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Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004; 01/2004
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ABSTRACT: We present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances for system-on-chip (SoC) designs. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that interlayer dummy metal fills have more significant influences than intralayer ones in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.
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ABSTRACT: In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance C eff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate C eff . In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of C eff . The introduction of Integration Approximation results in C eff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.
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ABSTRACT: In recent system-on-chip (SoC) designs, floating dummy metals inserted for planarization have created serious problems because of increased interconnect capacitance and the enormous amount of fill required. We present new methods to reduce the interconnect capacitance and the amount of dummy metals needed. These techniques include three ways of filling: 1) improved floating square fills, 2) floating parallel lines, and 3) floating perpendicular lines (with spacing between dummy metals above and below signal lines). We also present efficient simple formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the traditional regular square method was 13.1%, while that using the methods of improved square fills, extended parallel lines, and perpendicular lines was 2.5%, 2.4%, and 1.1%, respectively. Moreover, the number of necessary dummy metals can be reduced by two orders of magnitude through use of the parallel line method.
Quality Electronic Design, International Symposium on.