Atsushi KUROKAWA

Publications (19)0 Total impact

• Article: A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect.

  Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Qiang Li, Bin Lin, Yasuaki Inoue
  IEICE Transactions. 01/2011; 94-A:1201-1209.
• Article: Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies.

  Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue
  IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2010; 29:250-260.
• Article: Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model.

  Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Shuai Fang, Yasuaki Inoue
  IEICE Transactions. 01/2009; 92-A:2531-2539.
• Conference Proceeding: Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies.

  Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue
  Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007; 01/2007
• Conference Proceeding: Calculating the Effective Capacitance for Interconnect Loads Based on Thevenin Model

  Shuai Fang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue
  [show abstract] [hide abstract]
  ABSTRACT: Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance C_eff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to C_eff and RC-pi are not equal was not considered. With the progress of IC process technology, its influence on static timing analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation
  Communications, Circuits and Systems Proceedings, 2006 International Conference on; 07/2006
• Article: Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills.

  Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda
  IEICE Transactions. 01/2006; 89-A:847-855.
• Article: Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays.

  Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue
  IEICE Transactions. 01/2006; 89-A:856-864.
• Source

  Available from: google.com

  Article: Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay.

  Zhangcai Huang, Atsushi Kurokawa, Yun Yang, Hong Yu, Yasuaki Inoue
  IEICE Transactions. 01/2006; 89-A:840-846.
• Conference Proceeding: Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.

  Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda
  6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA; 01/2005
• Conference Proceeding: Effective capacitance for gate delay with RC loads.

  Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue
  International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan; 01/2005
• Article: Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew.

  Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue
  IEICE Transactions. 01/2005; 88-A:3367-3374.
• Conference Proceeding: Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills.

  Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda
  6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA; 01/2005
• Source

  Available from: jbnu.ac.kr

  Article: Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm.

  Yun Yang, Atsushi Kurokawa, Yasuaki Inoue, Wenqing Zhao
  IEICE Transactions. 01/2005; 88-A:3412-3420.
• Source

  Available from: jbnu.ac.kr

  Article: Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills.

  Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda
  IEICE Transactions. 01/2005; 88-A:3471-3478.
• Source

  Available from: osaka-u.ac.jp

  Article: Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance.

  Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda
  IEICE Transactions. 01/2005; 88-A:3453-3462.
• Conference Proceeding: DEPOGIT: dense power-ground interconnect architecture for physical design integrity.

  Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda
  Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004; 01/2004
• Source

  Available from: jbnu.ac.kr

  Article: A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills

  Atsushi KUROKAWA, Toshiki KANAMOTO, Akira KASEBE, Yasuaki INOUE, Hiroo MASUDA
  [show abstract] [hide abstract]
  ABSTRACT: We present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances for system-on-chip (SoC) designs. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that interlayer dummy metal fills have more significant influences than intralayer ones in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.
• Source

  Available from: jbnu.ac.kr

  Article: A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads

  Zhangcai HUANG, Atsushi KUROKAWA, Yasuaki INOUE, Junfa MAO
  [show abstract] [hide abstract]
  ABSTRACT: In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance C eff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate C eff . In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of C eff . The introduction of Integration Approximation results in C eff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.
• Article: Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills

  Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Chang Wei Fong, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda
  [show abstract] [hide abstract]
  ABSTRACT: In recent system-on-chip (SoC) designs, floating dummy metals inserted for planarization have created serious problems because of increased interconnect capacitance and the enormous amount of fill required. We present new methods to reduce the interconnect capacitance and the amount of dummy metals needed. These techniques include three ways of filling: 1) improved floating square fills, 2) floating parallel lines, and 3) floating perpendicular lines (with spacing between dummy metals above and below signal lines). We also present efficient simple formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the traditional regular square method was 13.1%, while that using the methods of improved square fills, extended parallel lines, and perpendicular lines was 2.5%, 2.4%, and 1.1%, respectively. Moreover, the number of necessary dummy metals can be reduced by two orders of magnitude through use of the parallel line method.
  Quality Electronic Design, International Symposium on.